Other Parts Discussed in Thread: AM3517
The AM3517 datasheet in section 3.5.1 has a very specific sequencing of
the power domains on the chip. The AM3517 datasheet shows the following for the power sequence:
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3.3-V Operation Sequence:
1. IO 1.8V (VDDS) supply should come up first. This is required to bias
the circuitry for the 3.3V IO's.
2. IO 3.3V (VDDSHV) supply should be ramped up next.
3. Band-gap, LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) should be
ramped up next.
4. Core supply follows next.
5. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST)
should be ramped
up next. Ensure PLL is powered-up in OFFMODE=1 to control any transients.
6. All the other complex IO power supplies should be ramped up next
(DAC, USB).
7. sys_nrespwron must be held low at the time the power supplies are
ramped up till the time the
sys_32k and sys_xtalin clocks are stable.
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Note that the VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU are #3 on the list.
However, on the EVM kit reference schematics I can see they are
powering this up at sequence #1 with the VDDS rail. Is this permissible?
Is there some other document that describes permissible power sequencing
that is different from what is in the AM3517 datasheet?
