Reset Management Confusion??

Hi Neki,

There is a short description about functions and difference between power domains which the CORE_DOM_RET_RST, CORE_RST_RET, CORE_RSTPWRON_RET and CORE_RST core power domains effects:

CORE_DOM_RET_RST - Asserted only for a power domain state transition from off to active state

CORE_RST_RET - Resets part of the SDRC, SDMA, SMS, MPU INTC, and IVA2 WUGEN

CORE_RSTPWRON_RET - Resets part of the SDRC and SCM

CORE_RST - Resets parts of the three asynchronous bridges, MPU INTC, IVA2.2 WUGEN, interconnects, ICR, modem INTC, SAD2D, mailboxes, GPMC, OCM, UART[1,2], HDQ, HS USB, I2C[1..3], McBSP 1 and 5, McSPI [1..3], MMC[1..3], GPTIMER[10,11]

Also you can get some clarification about reset destinations and and power reset management distribution from Fig 3-22 and Fig 3-25.

There is no implemented support of these registers in the u-boot but you can find their implementation in the kernel.

BR

Tsvetolin Shulev

Thanks Tsvetolin Shulev.

CORE_RST_RET
CORE_RSTPWRON_RET
CORE_RST

I want to know when each reset is asserted i.e under what conditions they get triggered like the one you said for CORE_DOM_RET_RST - Asserted only for a power domain state transition from off to active state.

I think one more reset is there too : CORE_DOM_RST.

where to find this triggering  information in Kernel?

Warm Regards

One new question:

where can i find the source code for ROM Bootloader code( OCM ROM)  that boots up CPU? I want to know what exactly this code does because I have to write BSP for Integrity RTOS.so I need to know in extra detail.

Hi Neki,

There is no implementation of the CORE_DOM_RST in the Kernel 2.6.37. You can obtain information about  the CORE_DOM_RST from the figures mentioned in my previous post.

The ROM Bootloader source code is not public and I think you could not find tis source code.

BR

Tsvetolin Shulev