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c6455 wasting bandwidth in SRIO 4x mode

ahmad abdol
Prodigy 20 points

there is a problem with 6455 SRIO in 4x mode.

i've connected c6455 to a vertix 6 FPGA, in 1x mode when i send 10 packet with length of 256 bytes and check the bus transaction on ChipOscope, there is 10 packet each with length of 256 bytes, but when i switch to 4x mode, there is 6 gaps inside of each packet which weren't exist in single lane mode. in other words, in single lane each packet have 256 bytes payload, but in 4x mode each packet have at least 6 other words which are from "SC" type. the code of these "SC" are 1C80FF0F (stype0 = buff_statue and stype1 = NOP ), there is no problem in receiving and sending, even in loopback mode, c6455 works properly and data reach its destination without any problem, the problem is these "SC" words which wasting one third of my bandwidth.

i already read all of the c6455 registers definition but i found nothing and i'm sure that the problem isn't inside FPGA (because in loopback mode FPGA is bypassed), could you help me please? (33% of band width is not something to deny)

clock = 125 MHz, Rate = 2.5 Gbps

  • 0
    TI__Guru* 84110 points

    This sounds like a signal integrity issue with the PHY having to do extra work to combat problems with the physical link.

    You said there are gaps "inside" of each packet. Do you mean to say "between" each packet, instead? I do not know what the PHY would be doing to insert another packet type in the middle of a 256-byte payload.

    If the FPGA is bypassed in loopback mode, how are you able to observe the extra packets on ChipOscope?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 20 points

    i've loopbacked it inside FPGA GTX not DSP, that's why i can use chiposcope. and could you please describe a little more. i mean is there anyway to overcome this problem by manipulating DSP SRIO registers?

  • 0 in reply to ahmad abdol
    TI__Guru* 84110 points

    Ahmad,

    Many many people have used DSP to FPGA over SRIO and have not had this problem. Your information so far is not complete enough to be convincing that this is a DSP problem and not an FPGA problem, since both are going through their respective PHYs. If you are using a reliable FPGA design, then the signal integrity on your board is more likely to be related to your problem.

    If you reduce the SRIO speed from 2.5GHz, do you get different results?

    Can you try a DSP internal loopback to see if the transactions take the same amount of time or not? If shorter by 1/3, then you will know something about the process and if the same length then you will know something about the process.

    Are there any relevant status or error flags set in the DSP or FPGA registers?

    Can you supply traces from ChipOscope to show the timing and occurrence of these packets, please?

    Information on the PHY packets and other physical layer activity is available in the RapidIO Physical Layer 1x/4x LP-Serial Specification available at rapidio.org.

    Regards,
    RandyP