I was wondering if you can help with the following questions.
1.
I am concerned about our CORECLK and DDRCLK sequence, the datasheet states;
And
Our clocks are under software control and come up after POR but before RESETFULL. I believed that RESETFULL was the same as POR but I am now not convinced. Is our implementation okay?
2. We have been encountering problems with pcie link up:
- pcie fails our training, resulting in link down.
- problem is intermittently on 2 out of 7 boards, not yet seen elsewhere;
- the main DSP clock is available as soon as DSP boots, but pcie clock is available only during kernel boot. The main PLL and PCIe PLL both properly locked prior to link failure;
- the problem can be lessen or worsen by playing with the timing and delay between the steps of either side. Adding delays sometimes makes it better, sometimes worse. However I haven't found a solution that gives 10 consecutive success.
Is there any known issues with this on single core. We did not see this with the eval cards.
