C6474　BOOT

In the Training section of TI.com, there is a training video set for the C6474. It will be helpful for you to review all of the modules. But in particular, the Memory & Cache Module and the Startup Considerations Module will apply to your current questions. You can find the video set at http://focus.ti.com/docs/training/catalog/events/event.jhtml?sku=OLT110002 .

For documentation, you will want to reference the datasheet SPRS552 and the Bootloader User's Guide SPRUEA7.

For each core, it has local L2 memory that is addressable by only that one core at address 0x00800000. But there is also a global address for each L2 memory that allows all cores to access it. For example, Core0 can access its L2 memory starting at the Local L2 address 0x00800000 and at the Global Address 0x10800000. Core1 and Core2 can also access Core0's L2 at address 0x10800000.

Thank you for answers.

I understood L2 memory.

Please teach it about a slave boot.

I want to boot DSP with FPGA.It is possible if I set boot mode in slave mode?

I add 7 bytes(slave address, length,checsum,boot option) to the top of data which I made at the time of I2C master boot and should send it to DSP?

 I refer to TMS320C645x/C647x DSP Bootloader User's Guide,

but,I do not understand it well.

Thanks.