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Address mapping

aichen wang
Intellectual 380 points

Hi, everyone!

         I want to write data to DDR from PC. I have some doubts about mapping address to DDR. In my procedure, this is the address mapping:

                             m_MemoryRange0.outd(IB_OFFSET(3),DDR_START)

and the size of the region 3 is 16M, the value of DDR_START is 0x80000000.

        So I want to know whether I can just write data to (read data from) DDR from 0x80000000 to 0x80FFFFFF?

       The board is EVM6678 and the PC is XP.

      Hope someone give me any suggestion as soon as possible!

Thanks !

  • 0
    TI__Mastermind 28085 points

    Hi Aichen,

    Please provide more detail about your test setup? I think you connect the EVM card to PC via PCIe interface and access the DDR memory from windows driver.

    For my understanding TI not provide windows based example driver code for testing DDR (read/write).

    TI provide Linux based example driver code for this testing. Please take a look at below file in TI MCSDK package

    \ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader\pciedemo.c

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 380 points

    Hi,

        Your understanding is right. I connect the EVM card to PC via PCIe interface, and the code refers to

              \ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader\pciedemo.

                                   uint32_t writeDSPMemory(uint32_t coreNum, uint32_t DSPMemAddr, uint32_t *buffer, uint32_t length) 

                                  uint32_t readDSPMemory(uint32_t coreNum, uint32_t DSPMemAddr, uint32_t *buffer, uint32_t length) 

    .

            So I want to know if the bar3 is mapped to DDR from 0x80000000 and the size of bar3 is 16MB, could I be able to write data to DSP from 0x90000000?

    Regards!

    wang aichen

     

  • 0 in reply to aichen wang
    TI__Mastermind 28085 points

    Hi Aichen,

    Yes, you able to write the data to DSP(DDR3 address) from 0x90000000.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 230 points

    Hi,

        I don't think this is possible.

         Aichen, I don't think an Inbound ATU has a limitation in size. And the '16MB' is acturally for BAR3, nor IB_XXX(3), correct ?

        If the size of BAR3 is 16MB and it's redirected by IB_XXX(3) to the BASE of DDR, you can only read/write within the range of BAR3 and any operation beyond the range will be rejected by BAR3 (may still be accepted by other BARs).  If you need to read from 0x90000000, you can redirect the ATU dynamically via BAR0, just like what the pciedemo.c does.

    Ganapathi Dhandapani said:

    Hi Aichen,

    Yes, you able to write the data to DSP(DDR3 address) from 0x90000000.

    Thanks,

  • 0 in reply to Hawk Chan
    Intellectual 380 points

    Hi,

    Thanks for your replies.

    In fact, I can write data to 0x90000000 and read the same data which I write from 0x90000000, but when i watch the memory from CCS, the data from 0x90000000 is not what i have written.

    So, Hawk Chan,can  you explain that phenomenon to me?

    Expect to receive your reply!

    Regards,

    wang aichen

  • 0 in reply to aichen wang
    Prodigy 230 points

    Hi,

       Could you please check the configuration for all the BARs and Inbound ATUs and paste it here ?

       Consider for the following two possibilities:

        (1) In fact, you are not writing to 0x90000000 but some other valid memory region (MMRs, L2 or a different offset of DDR) due to unexpected ATU configuration.

        (2) You write to 0x90000000 successfully and the data is in physical memory (DDR) and you are reading from the cache. To verify this, simply uncheck the "L1D" and "L2"checkbox in the memory browser in CCS.

        Chinese, aha? We are struggling in the same pool which is named PCIe ... I think we should use QQ instead, see my personal profile and contact me~

        Regards

        Hawk