• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 551 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

FPGA - DSP communication for GSM IQ samples

Manimaran Subramanian
Prodigy 30 points

Dear All

I am planning to use C6474 for GSM demodulation. The overall system should be capable of receiving 30+ channels. FPGA - DSP communication will be used for transferring IQ samples for further processing.

My question:

1. What is suitable interface (SRIO/AIF/any other) for FPGA - DSP interface for receiving 30 channels IQ samples from FPGA to DSP. I am planning to use only one DSP.

2. What is the suggested data rate.

Regards

S Manimaran

 

 

 

  • 0
    TI__Guru* 84110 points

    The AIF is intended for transferring data, so it would certainly be a good choice. It is a very complex peripheral, so expect a steep learning curve. But if you are doing GSM demod, you have to be pretty advanced already.

    SRIO is also a good link to use, but it has more overhead in the FPGA to implement the SRIO protocol. Both AIF and SRIO use SERDES signals for high-speed data transfer.

    The link rates are specified in the datasheet.