How OMAP4 RFBI works

Hello Vikram,

#Q1: is in RFBI do we need to use write back pipeline.

I don't think that you must use WB pipeline. There is no such requirements.

The input video port FIFO receives data from the DISPC at the pixel clock. The data in the video port FIFO are read by the RFBI and sent to the LCD panel.

RFBI Output Parallel Modes, provides examples of various output configurations based on the interface width (up to 16 bits) and pixel format output (up to 24 bits). Setting the RFBI_CONTROL[1] RFBIMODE bit to 0 directs the MPU to send commands, parameters, and data from the input video port FIFO.

The fullness of the FIFOs associated with the pipelines used for the LCD output is checked when the STALL signal is inactive before providing data to the pipeline. This prevents emptying the FIFO when the RFBI requests data and there is not enough data in the DISPC DMA buffer. This feature must be enabled only when stall mode is used
(DISPC_CONTROLo[11] STALLMODE bit set to 1).

See the /drivers/video/omap2/dss/ rfbi.c - RFBI driver

#Q2: So, is this means that after combining all overlay frame stores in memory and using RFBI it will send to lcd.
The DISPC supports two LCD outputs and one TV output - each one with a dedicated overlay manager.

The DISPC allows capturing of one output of the pipeline or overlay manager to redirect it into the WB pipeline. It allows to take benefit of the hardware processing available inside the DISPC like color space conversion, rescaling, compositing, etc., to perform memory-to-memory transfer with data processing.
The DMA engine in DSS - Stores (encoded pixel data) from the GFX/VID pipelines or overlays to memories through the WB pipeline and interconnect based on the configuration of the DISPC and WB pipeline settings.

If it is necessary to be used writeback pipeline (WB), there are two modes supported by WB channels:

- Capture mode, WRITEBACKMODE bit set to 0: One of the overlay outputs going to LCD or TV outputs is captured and at the same time the data are sent on the output. The WB timings are controlled by the LCD or TV timings.
- Memory-to-memory mode, WRITEBACKMODE bit set to 1: One of the overlay outputs or one of the pipelines is captured to perform memory-to-memory transfer with some processing by the DISPC (rescaling, overlaying, color space conversion, etc.).

The data are read by the DISPC from the memory frame buffer (SDRAM, SRAM, IVA-HD SL2, etc.), and sent through the RFBI to the external LCD/RFB.
The DISPC associated with the RFBI implements the MIPI DBI protocol.
The DISPC provides the required control signals to interface the memory frame buffer (SDRAM, SRAM or IVAHD-SL2) directly to the external displays. The RFBI is connected to the memory through the L3 interconnect and has its own DMA (with embedded FIFOs) to read data from the system memory. There is one master port (L3 interconnect) and two slave ports (one for L4_PER interconnect and the other for L3 interconnect).

Best regards,

Yanko

Hi Yanko,

Thanks for direction.

I already check RFBI_ICLK it's 200Mhz.I think slow refresh rate is due to lcd1_pclk(26Khz) only.

After some debugging in RFBI releted clock section , i come across these clk settings:

- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK)
fck             170666666
- DISPC-CORE-CLK -
lck             170666666       lck div 1
- LCD1 -
lcd1_clk source = DSS_FCK (DSS_FCLK)
lck             1777777         lck div 96
pck             26143           pck div 68
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck             42666666        lck div 4
pck             42666666        pck div 1

Look like lcd1 output redirect to RFBI and pclk of lcd 1 is just 26Khz and my data rate to lcd from rfbi is around 25-26 Khz.

After reading from TRM i found that Pclk is pixel clock used by RFBI to capture pixel from DISPC.

By changing Pclk for lcd1 , should i need to change lcd1_fclk for RFBI and is Pclk is depend on timing control parameter(CS , WE and RE) of RFBI?

As u mention to check the refresh rate , hsync and vsync--> i am not using these lines, using internal trigger mode so after getting FRAMEDONE_IRQ again start sending another frame.Just send frame into lcd's framebuffer with lcd ac timings.

Thanks for ur support

Vikram

Hi all,

I got solution.

It's because lcd1 pclk and lcd1 fclk. I changes it and i got 15 fps.

Thanks

Vikram