Hi
i am using 122.88 MHz clock for my DSP processor(TMS320C6674).
The CPU need to run with 1GHz clock.Is i am able to generate the 1GHz clock by using the 122.88 MHz input frequency.
Please provide the PLL clock formula.
Please let me know,your suggestion.
Regards,
srinivasarao
Hi Srinivasarao,
Please refer the section "PLL Boot Configuration Settings" of device data manual (http://www.ti.com/lit/ds/symlink/tms320c6674.pdf) for more information.
OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting for the device (with OUTPUT_DIVIDE=1, by default).
CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
Keystone PLL User Guide: http://www.ti.com/lit/ug/sprugv2f/sprugv2f.pdf
Thanks.
