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MSI interrupt information

zakaria-kech
Prodigy 40 points

Hello,

  We are using PCIe interface of our 6678 DSP. We have configured one C6678 as Root Complex and another C6678 as End Point using a BOC.

I use MSI interrupt and i I succeeded the test, and I found many subject in this forum, but now I want to understand the principle of these interruptions, and the philosophy to manage different groups and vectors of MSI interrupt.

1- why has exactly eight MSI group in C6678, this is indicated in the specification, or or just because it has eight cores in C6678?

2- " PCIExpress_MSI_INTn is connected to CorePac_n in C6678...."   By Steven Ji

"connected" in this sentence, mean connected by hardware or just software?

3- What is the treatment carried out in the PCIESS to identify the GROUPE MSI0, MSI1...MSI1 ?

Thanks in advance,

Sincerely,


Franc.

 

  • 0
    Intellectual 460 points

    Hi Franc,

    I used too nearly the same scenario, with the same devices, so I can give you some answers:

    1- I think juut because the DSP 6678 has eight cores, and I found nothing apropo this topic in the specification.

    2-  I  think just software

    3- I have no idea

     

    but all these answers, it's just my point of view.

    your questions are very important, I waiting too the answers from TI Employee.

    Regards,

    Zakaria

     

  • 0 in reply to kchakechk zakaria
    TI__Mastermind 28085 points

    Hi Franc,

    Ans1: C6678 device have 8 cores, each core will receive separate MSI INTs, that only C6678 have exactly eight MSI group. CorePac 0 will only receive interrupt from MSI_0 (vectors 0/8/16/24). Similarly, Core1 will receive MSI_1 (vectors 1/9/17/25), Core 7 will receive MSI_7, etc.

    Ans2: PCIExpress_MSI_INTn is connected to CorePac_n in C6678. MSI0 is connected to CorePac0 and only, In software you need to enable the enabled MSI INT and determine the number of MSI vectors allocated (and the number requested) to the device.  

    The user software is required to acknowledge the serviced interrupt.

    I am not clear on your third question, please give more detail.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 40 points

    Hi everyone,

    Thanks Zakaria and Ganapathi for your answers.

    to give you more detail:

    for example when I send MSI1 (1,9,17,25) it will be processed at the core1 only, why exactly it is visible just on the core 1 not core 0..., ?

    ie is that possible to treat other vectors such as (1,5,16, ..) on the core0?

     

    Thanks, Sincerely,


    Franc.

     

  • 0 in reply to zakaria-kech
    TI__Mastermind 28085 points

    Hi Franc,

    If you want to use MSI interrupt to another core means you may need to add software workaround if you want one CorePac to service the interrupts from other CorePacs (such as IPC, that CorePac_x notify CorePac_y when CorPac_x receives MSI_INT_x).

    It is not possible, such vectors are dedicated to specific MSI Interrupt.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 40 points

    Thanks Ganapathi,

    I have one last question :

    you said that "CorePac 0 will only receive interrupt from MSI_0 (vectors 0/8/16/24). Similarly, Core1 will receive MSI_1 (vectors 1/9/17/25), Core 7 will receive MSI_7, etc."

    you said also MSI is redirected just by software no by hardware.

    ==> so when the EP send MSIn to RC. How RC will do to distinguish between MSI0, MSI1 .. MSI7? for order to redirecting the interruption to the right distination (core).

    Thanks again,

    Franc,

  • 0 in reply to zakaria-kech
    TI__Mastermind 28085 points

    Hi Franc,

    The memory write transactions to generate MSI interrupts in RC are actually targeted at MSI_IRQ register. The MSI interrupt is generated as a result of the one of 32 events that is triggered by a write of MSI vector value to MSI_IRQ register in RC. Before the end point devices can issue MSI interrupts, the MSI address and data registers must be
    configured by system software to make sure the MSI_IRQ registers could be accessed correctly with proper MSI vector value.

    If you need more information please refer PCIe user guide (SPRUGS6D).

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 40 points

    Hi Ganapathi,

    Thanks  for your answer, I think I haven't been clear in my question, I already know the principle of the interruptionMSI. But the problem I did not understand when when the interrupt is generated (EP==> RC). which will prevents it for it will be visible on other cores

    Example: when I generate MSI1 EP to RC: this MSI it will be visible right in the RC(core1), why not the other cores?

    What is the treatment that will leave this intteruption is visible on a core, and not visible in other cores?

     

    Thanks, Sincerely,


    Franc.

     

     


  • 0 in reply to zakaria-kech
    TI__Mastermind 28085 points

    Hi Franc,

    I do not have too much experience on MSI Interrupt.

    My understanding such MSI Interrupt are dedicated to specific core in SOC level. It is not possible to visible to other cores.  

    If you want to use MSI interrupt to another core means you may need to add software workaround if you want one CorePac to service the interrupts from other CorePacs (such as IPC, that CorePac_x notify CorePac_y when CorPac_x receives MSI_INT_x).

    Thanks,