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I've connected 2 C6678 DSP via Hyperlink.
in each the code enables the power domain and setup the SERDES.
The 1st DSP try to configure the register in remote but then the code crash and a message error says that the core is hung
What could be the problem?
From the Hyperlink Status Register i see that bit 8 (Remote error) and bit 7 (Local error) are both set.
I've also tryed to setp the 2 DSP using only local registers but it seems that hyperlink isn't working
Hi Gabriele,
My suggestion would be try with Hyperlink example project available in MCSDK.
MCSDK(02_01_02_06): http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html
MCSDK UG: http://processors.wiki.ti.com/index.php/BIOS_MCSDK_2.0_User_Guide
Example Project Path: ..\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\hyplnk_exampleProject
Thanks.
Hi
I've installed MCSDK but when i try to import the Hyperlink example project i get some errors
Unrecognized product of type 'com.ti.sdo.edma3' is required by project 'hyplnk_exampleProject' - please install at least one product of this type before building this project.
Unrecognized product of type 'com.ti.rtsc.IPC' is required by project 'hyplnk_exampleProject' - please install at least one product of this type before building this project.
Unrecognized product of type 'com.ti.biosmcsdk.pdk.C6657' is required by project 'hyplnk_exampleProject' - please install at least one product of this type before building this project.
Hi,
From my understanding, You have not re-started the CCS after MCSDK installation or not installed the MCSDK in default installation directory. Due to which the CCS not recognized the products installed on it.
Our recommendation is to install all the packages on default installation directory. The new products discovered page will look like below.
Please add tool discovery path and refresh the discovered tools from Window->Preferences->CCS->RTSC->Products.
Thanks.
However, i've done some other test with my code.
If i enable the LOOPBACK the code work correctly. I can see the remote register (that are the local...) and write in hyperlink data section seeing the data copied in the shared memory as i've programmed
If i disable the LOOPBACK I've also seen from HyperLink SerDes Status Register that the 4 lanes are under-equalized. Could be this the problem?
Because Status Register says that the serial interface initialization sequence has completed successfully (BIT 0 (Link) = 1) but just after the inizialization sequence i see setted the bit of local error and remote error and also the bit nfempty1 that indicates that the Master Command FIFO is not empty.
Hi,
Please refer the Hyperlink User Guide for more information. Refer section 2.6 SerDes Configuration and Clocking & HyperLink SerDes Programming Example.
Thanks.
Yes, yes, i've used the example in the hyperlink documentation for my inizialization
bool CHYPERLINK::Enable()
{
/* Hyperlink power domain is turned OFF by default. It needs to be turned on before doing any Hyperlink device register access. */
// 1. Set Hyperlink Power domain to ON
prPSC_PDCTL[5] = 1; //Hyperlink = Power Domain n.5
// 2. Enable the clocks too for Hyperlink
prPSC_MDCTL[12] |= 3; //Hyperlink = Module Control Register n.12
// 3. Start the state transition
rPSC_PTCMD |= (1 << 5); //Hyperlink = Power Domain n.5
// 4. Wait until the state transition process is completed
while ( rPSC_PDTSTAT & (1<<5) ) ;
// 5. Check Hyperlink PSC status
bool PowerDomainState = prPSC_PDSTAT[5] & 3;
UINT32 ModuleState = prPSC_MDSTAT[12];
if (PowerDomainState && (ModuleState & 3) )
return true; /* Hyperlink ON. Ready for use */
else
return false; /* Hyperlink Power on failed. Return error */
}
void CHYPERLINK::Setup()
{
volatile int i;
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* ERRATA - HyperLink Data Rate Limited to 40 Gbaud Issue *
* The HyperLink interface is currently limited to a maximum transfer rate of 10 Gbaud per lane (40 Gbaud for four lanes) *
* due to a SerDes PLL limitation. *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
// 1. Place peripheral into reset
pSiHYPLNK_LOCAL_REGS->ctrl |= 1;
// 2. Unlock the Boot Configuration Kicker
KICKUNLOCK()
// 3. HyperLink SerDes PLL Register Configuration
/*LINERATE=REFCLK*MPY/RATESCALE PLL_OUTPUT=REFCLK*MPY must be in the 1.5625 GHz to 3.125 GHz range.*/
/*MPY = 16, RATESCALE = 0,25 (Full Rate) => LINERATE = 10 Gbaud*/
rHYPLNK_SERDES_CFGPLL = (0 << 11) | //Loop bandwidth = 0 = Medium Bandwidth (Recommended)
(0 << 9) | //Voltage Controlled Oscillator Range = 0 (PLL_OUTPUT = 2.5GHz > 2.17GHz)
(0x40 << 1) | //01000000b -> MPY = 16 -> for 156.25MHz sets PLL_OUTPUT to 2,5GHz
(0 << 0); //PLL Disabled (This value is set automatically by the HyperLink module based on the RESET bit in the CONTROL register.)
// 4. Wait till the Hyperlink PLL is locked
while ( (rHYPLNK_SERDES_STS & 1) == 0 ) ;
// 5.Configure HyperLink SerDes Receive Registers
for (i=0;i<4;i++)
rHYPLNK_SERDES_CFGRX(i) = (0 << 23) | //LOOPBACK disabled
(1 << 22) | //Enable offset compensation. Always set to 1 to enable offset compensation.
(0 << 21) | //Hold equalizer. Always set to 0 to enable equalizer adaptation and analysis.
(1 << 18) | //Equalizer = 001b (fully adaptive)
(5 << 15) | //Clock/data recovery = 101b = First order (Recommended)
(4 << 12) | //Loss of signal detection = 100b (Enabled)
(0 << 10) | //Symbol alignment. This field is set automatically by the HyperLink module.
(1 << 7) | //TERM = 001b for AC coupling
(0 << 6) | //Normal polarity.
(0 << 4) | //RATE = 00b full rate
(2 << 1) | //Bus width. Fixed to 010b
(1 << 0); //Enable receiver
// 6. Configure HyperLink SerDes Transmit Registers
for (i=0;i<4;i++)
rHYPLNK_SERDES_CFGTX(i) = (0 << 21) | //LOOPBACK disabled
(1 << 20) | //Synchronization master
(1 << 19) | //Transmitter pre and post cursor FIR filter update. This field should always be set to 1.
(0x17 << 14) | //Adjacent post cursor Tap weight = 10111b for traces with less than 4” between devices
(4 << 11) | //Precursor Tap weight = 100b (Recommended starting value)
(7 << 7) | //Output swing = 0111b (Recommended starting configuration)
(0 << 6) | //Normal polarity.
(0 << 4) | //RATE = 00b full rate
(2 << 1) | //Bus width. Fixed to 010b
(1 << 0); //Enable receiver
// 7. Lock the Boot Configuration Kicker
KICKLOCK()
// 8.Reset the peripheral
pSiHYPLNK_LOCAL_REGS->ctrl |= 1;
// 9. Clear any error
pSiHYPLNK_LOCAL_REGS->status = (1 << 8) | (1 << 7);
pSiHYPLNK_LOCAL_REGS->ecc_err_cnt = 0;
// 10. Enable Four Lane Mode
pSiHYPLNK_LOCAL_REGS->lane_pwrmgm = 1 << 2;
// 11. Setup SerDes Control and Status Register 1
pSiHYPLNK_LOCAL_REGS->serdes_ctrl_1 = (0xFF << 24) | //SerDes sleep mask count
(0xFF << 16); //SerDes disable mask count
// 12. Setup Interrupt
pSiHYPLNK_LOCAL_REGS->ctrl |= (1 << 14) | //Interrupt Local = 1 -> interrupts are posted in the Interrupt Status/Clear Register
(1 << 13) | //Interrupt Enabled
(0 << 8) | //Interrupt Vector (indicates which bit in the Interrupt Pending/Set Register is set)
(0 << 7); //Interrupt to Configuration Register.
// 13.Take out of reset
pSiHYPLNK_LOCAL_REGS->ctrl &= ~1;
// 14. Wait for peripheral to come up
while ( (pSiHYPLNK_LOCAL_REGS->status & ((1 << 13)|(1 << 12)|(1))) != 1 ) ; //Repeat until serial_halt = 0, pll_unlock = 0, link = 1
// 15. Reset the segment counter
ms_SegmentCounter = 0;
}
Is there some guidelines to follow to found and set the ideal values of the Output Swing and the Precursor Tap Weight?
Or should I go by trial and error until i see that the Lanes arent't over-equalized or under-equalized?
I've finally executed the example code hyplnk_exampleProject and this is the console report:
[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:27:45
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000080; RX=0x0046c485; TX=0x000d0c05
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up ( 0)
SERDES_STS (32 bits) contents: 0x03468d1b; lock = 1
Waiting for other side to come up ( 1)
Waiting for other side to come up ( 2)
[C66xx_8] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:27:45
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000080; RX=0x0046c485; TX=0x000d0c05
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
SERDES_STS (32 bits) contents: 0x00081021; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cff
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Local before stability wait status.lError = 1
Local before stability wait status.rError = 1
Local before stability wait WARNING: ECCErrors.sglErrCor = 58438
Local before stability wait ECCErrors.dblErrDet = 1
[C66xx_0] SERDES_STS (32 bits) contents: 0x00000001; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cf0
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Local before stability wait status.lError = 1
Local before stability wait status.rError = 1
Local before stability wait WARNING: ECCErrors.sglErrCor = 28197
Local before stability wait ECCErrors.dblErrDet = 1
Hi Gabriele,
This is the expected log for MCSDK Hyperlink example project. But It is not successfull test log, you got some errors on the serial link on local side.
Have you modified the MCSDK Hyperlink example project?
I have attached the Hyperlink example project log file(loopbak and non loopback mode test) for your reference. please make sure the hyplink connection between two DSPs for non loopback mode test.
[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:04:15 [C66xx_0] About to do system setup (PLL, PSC, and DDR) [C66xx_0] Power domain is already enabled. You probably re-ran without device reset (which is OK) [C66xx_0] Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305 [C66xx_0] system setup worked [C66xx_0] About to set up HyperLink Peripheral [C66xx_0] ============== begin registers before initialization =========== [C66xx_0] Revision register contents: [C66xx_0] Raw = 0x4e901900 [C66xx_0] Status register contents: [C66xx_0] Raw = 0x00002004 [C66xx_0] Link status register contents: [C66xx_0] Raw = 0x00000000 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00000001 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00000000 [C66xx_0] ============== end registers before initialization =========== [C66xx_0] Waiting for other side to come up ( 0) [C66xx_0] SERDES_STS (32 bits) contents: 0x02048819; lock = 1 [C66xx_0] Waiting for other side to come up ( 1) [C66xx_0] SERDES_STS (32 bits) contents: 0x03068c19; lock = 1 [C66xx_0] Waiting for other side to come up ( 2) [C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:04:15 [C66xx_0] About to do system setup (PLL, PSC, and DDR) [C66xx_0] Power domain is already enabled. You probably re-ran without device reset (which is OK) [C66xx_0] Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305 [C66xx_0] system setup worked [C66xx_0] About to set up HyperLink Peripheral [C66xx_0] ============== begin registers before initialization =========== [C66xx_0] Revision register contents: [C66xx_0] Raw = 0x4e901900 [C66xx_0] Status register contents: [C66xx_0] Raw = 0x00002004 [C66xx_0] Link status register contents: [C66xx_0] Raw = 0x00000000 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00000001 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00000000 [C66xx_0] ============== end registers before initialization =========== [C66xx_0] SERDES_STS (32 bits) contents: 0x00000001; lock = 1 [C66xx_0] ============== begin registers after initialization =========== [C66xx_0] Status register contents: [C66xx_0] Raw = 0x04400005 [C66xx_0] Link status register contents: [C66xx_0] Raw = 0xccf00cff [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00006200 [C66xx_0] ============== end registers after initialization =========== [C66xx_0] Waiting 5 seconds to check link stability [C66xx_0] Waiting for other side to come up ( 3) [C66xx_0] SERDES_STS (32 bits) contents: 0x0c183061; lock = 1 [C66xx_0] ============== begin registers after initialization =========== [C66xx_0] Status register contents: [C66xx_0] Raw = 0x04400005 [C66xx_0] Link status register contents: [C66xx_0] Raw = 0xfdf0bdf0 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00006200 [C66xx_0] ============== end registers after initialization =========== [C66xx_0] Waiting 5 seconds to check link stability [C66xx_0] Precursors 0 Analysis: 0,1,0,1,1,0,0,1 [C66xx_0] Postcursors: 19 Analysis: 0,1,1,0,0,1,0,1 [C66xx_0] Link seems stable [C66xx_0] About to try to read remote registers [C66xx_0] ============== begin REMOTE registers after initialization =========== [C66xx_0] Status register contents: [C66xx_0] Raw = 0x0440000b [C66xx_0] Link status register contents: [C66xx_0] Raw = 0xfdf0bdf0 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00006200 [C66xx_0] ============== end REMOTE registers after initialization =========== [C66xx_0] Peripheral setup worked [C66xx_0] About to read/write once [C66xx_0] Precursors 0 Analysis: 0,1,0,1,0,1,0,1 [C66xx_0] Postcursors: 19 Analysis: 1,0,1,0,0,1,0,1 [C66xx_0] Link seems stable [C66xx_0] About to try to read remote registers [C66xx_0] ============== begin REMOTE registers after initialization =========== [C66xx_0] Status register contents: [C66xx_0] Raw = 0x0440000b [C66xx_0] Link status register contents: [C66xx_0] Raw = 0xfdf0bdf0 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00006200 [C66xx_0] ============== end REMOTE registers after initialization =========== [C66xx_0] Peripheral setup worked [C66xx_0] About to read/write once [C66xx_0] Single write test passed [C66xx_0] About to pass 65536 tokens; iteration = 0 [C66xx_0] Single write test passed [C66xx_0] About to pass 65536 tokens; iteration = 0 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141829 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 1 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141830 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 1 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141841 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 2 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141841 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 2 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141824 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 3 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141825 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 3 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141804 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 4 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141805 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 4 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141843 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 5 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141844 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 5 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141821 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 6 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141822 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 6 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141831 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 7 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141832 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 7 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141812 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 8 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141812 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 8 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141808 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 9 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141809 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 9 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141804 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 10 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141805 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 10 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141844 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 11 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141844 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 11 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141841 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 12 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141841 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 12 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141835 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 13 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141835 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 13 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141805 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 14 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9293 Mcycles [C66xx_0] Approximately 141806 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 14 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141822 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 15 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141823 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 15 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9291 Mcycles [C66xx_0] Approximately 141781 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 16 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9291 Mcycles [C66xx_0] Approximately 141782 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 16 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9292 Mcycles [C66xx_0] Approximately 141799 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 17 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9292 Mcycles [C66xx_0] Approximately 141799 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 17 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141840 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 18 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9295 Mcycles [C66xx_0] Approximately 141840 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 18 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141816 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 19 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 9294 Mcycles [C66xx_0] Approximately 141817 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 19 The maximum size per LSU transfer block is 1MB, if transfer->byteCount larger than 1MB, this function only submit transfer for 1MB. After transfer submission, the transfer->byteCount is decreased to indicate the remaining bytes, the transfer addresses are increased to indicate the start address for next possible transfer. The caller can check these to take proper action.Transcation ID and context bit are recorded in transfer->transactionID and transfer->contextBit for caller to check completion status.
[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:04:15 About to do system setup (PLL, PSC, and DDR) Power domain is already enabled. You probably re-ran without device reset (which is OK) Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305 system setup worked About to set up HyperLink Peripheral ============== begin registers before initialization =========== Revision register contents: Raw = 0x4e901900 Status register contents: Raw = 0x00002004 Link status register contents: Raw = 0x00000000 Control register contents: Raw = 0x00000001 Control register contents: Raw = 0x00000000 ============== end registers before initialization =========== SERDES_STS (32 bits) contents: 0x00000001; lock = 1 ============== begin registers after initialization =========== Status register contents: Raw = 0x04400005 Link status register contents: Raw = 0xccf00cf0 Control register contents: Raw = 0x00006202 ============== end registers after initialization =========== Waiting 5 seconds to check link stability Precursors 0 Analysis: 1,0,1,0,0,1,1,0 Postcursors: 19 Analysis: 1,0,1,0,1,0,1,0 Link seems stable About to try to read remote registers ============== begin REMOTE registers after initialization =========== Status register contents: Raw = 0x0440080f Link status register contents: Raw = 0xfdf0bdf0 Control register contents: Raw = 0x00006202 ============== end REMOTE registers after initialization =========== Peripheral setup worked About to read/write once Single write test passed About to pass 65536 tokens; iteration = 0 === this is not an optimized example === Link Speed is 4 * 6.25 Gbps Passed 65536 tokens round trip (read+write through hyplnk) in 16220 Mcycles Approximately 247508 cycles per round-trip === this is not an optimized example === Checking statistics About to pass 65536 tokens; iteration = 1 === this is not an optimized example === Link Speed is 4 * 6.25 Gbps Passed 65536 tokens round trip (read+write through hyplnk) in 16220 Mcycles Approximately 247508 cycles per round-trip === this is not an optimized example === Checking statistics About to pass 65536 tokens; iteration = 2
Thanks,
I've only checked the defines for the parameters used in the project (clock, speed...)
but i've not changed the code
Gabriele
Hi Gabriele,
Please try to run the hyperlink example project to single EVM with loopback mode.
Uncomment the "#define hyplnk_EXAMPLE_LOOPBACK" line in hyplnkLLDCfg.h file.
Thanks,
i've already tryed, in loopback the project is running but i stil need to know why i cant connect the 2 DSP.
Also in my project i've tryed dofferent values of precursor, poscursor, swing to find a better setting but i continue to see the flag of local error and remote error.
With some values i can temporarily access to remote registers or to the memory shared by hyperlink but it seems very unstable ad after some reading i get the message that the core is hung and i always see the flag for local and remote errors and a lot of errors in Error Counters Register
I've tryed a different configuration using the lowest possible speed: 1 lane, speed 1,250 Gbps and now it seems it's working
[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:27:45
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000080; RX=0x0046c4b5; TX=0x000807b5
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up ( 0)
SERDES_STS (32 bits) contents: 0x03068c1d; lock = 1
Waiting for other side to come up ( 1)
[C66xx_8] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:27:45
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000080; RX=0x0046c4b5; TX=0x000807b5
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
SERDES_STS (32 bits) contents: 0x00000001; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cf0
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
[C66xx_0] SERDES_STS (32 bits) contents: 0x00000001; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cff
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
[C66xx_8] Precursors 0 Analysis: 1,0,0,0,0,0,0,0
Postcursors: 0 Analysis: 0,1,0,0,0,0,0,0
Link seems stable
About to try to read remote registers
============== begin REMOTE registers after initialization ===========
Status register contents:
Raw = 0x0440000b
Link status register contents:
Raw = 0x55105510
Control register contents:
Raw = 0x00006200
============== end REMOTE registers after initialization ===========
Peripheral setup worked
About to read/write once
[C66xx_0] Precursors 0 Analysis: 1,0,0,0,0,0,0,0
Postcursors: 0 Analysis: 0,1,0,0,0,0,0,0
Link seems stable
About to try to read remote registers
============== begin REMOTE registers after initialization ===========
Status register contents:
Raw = 0x0440000b
Link status register contents:
Raw = 0x55105510
Control register contents:
Raw = 0x00006200
============== end REMOTE registers after initialization ===========
Peripheral setup worked
About to read/write once
Single write test passed
About to pass 65536 tokens; iteration = 0
[C66xx_8] Single write test passed
About to pass 65536 tokens; iteration = 0
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Link Speed is 1 * 1.25G Gbps
[C66xx_8] Link Speed is 1 * 1.25G Gbps
[C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 17320 Mcycles
[C66xx_8] Passed 65536 tokens round trip (read+write through hyplnk) in 17320 Mcycles
[C66xx_0] Approximately 264282 cycles per round-trip
[C66xx_8] Approximately 264282 cycles per round-trip
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Checking statistics
[C66xx_8] Checking statistics
[C66xx_0] About to pass 65536 tokens; iteration = 1
[C66xx_8] About to pass 65536 tokens; iteration = 1
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Link Speed is 1 * 1.25G Gbps
[C66xx_8] Link Speed is 1 * 1.25G Gbps
[C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 17320 Mcycles
[C66xx_8] Passed 65536 tokens round trip (read+write through hyplnk) in 17320 Mcycles
[C66xx_0] Approximately 264282 cycles per round-trip
[C66xx_8] Approximately 264282 cycles per round-trip
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Checking statistics
[C66xx_8] Checking statistics
[C66xx_0] About to pass 65536 tokens; iteration = 2
[C66xx_8] About to pass 65536 tokens; iteration = 2
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Link Speed is 1 * 1.25G Gbps
[C66xx_8] Link Speed is 1 * 1.25G Gbps
[C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 17319 Mcycles
[C66xx_8] Passed 65536 tokens round trip (read+write through hyplnk) in 17319 Mcycles
[C66xx_0] Approximately 264269 cycles per round-trip
[C66xx_8] Approximately 264269 cycles per round-trip
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Checking statistics
[C66xx_8] Checking statistics
[C66xx_0] About to pass 65536 tokens; iteration = 3
[C66xx_8] About to pass 65536 tokens; iteration = 3
While the same speed with 4 lane mode has given this result
[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:27:45
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000080; RX=0x0046c4b5; TX=0x000807b5
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up ( 0)
SERDES_STS (32 bits) contents: 0x03060c1d; lock = 1
Waiting for other side to come up ( 1)
[C66xx_8] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:27:45
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000080; RX=0x0046c4b5; TX=0x000807b5
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
SERDES_STS (32 bits) contents: 0x00000001; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cf0
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
[C66xx_0] Waiting for other side to come up ( 2)
SERDES_STS (32 bits) contents: 0x04081021; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xfdf0bdf0
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
[C66xx_8] Precursors 0 Analysis: 0,0,1,0,1,0,0,0
Postcursors: 0 Analysis: 0,1,0,1,0,1,0,1
Link seems stable
About to try to read remote registers
============== begin REMOTE registers after initialization ===========
Status register contents:
Raw = 0x0440000b
Link status register contents:
Raw = 0xfdf0bdf0
Control register contents:
Raw = 0x00006200
============== end REMOTE registers after initialization ===========
Peripheral setup worked
About to read/write once
[C66xx_0] Precursors 0 Analysis: 1,0,1,0,1,0,1,0
Postcursors: 0 Analysis: 0,1,0,1,0,1,0,1
Link seems stable
About to try to read remote registers
============== begin REMOTE registers after initialization ===========
Status register contents:
Raw = 0x0440080f
Link status register contents:
Raw = 0xfdf0bdf0
Control register contents:
Raw = 0x00006200
============== end REMOTE registers after initialization ===========
Peripheral setup worked
About to read/write once
Single write test passed
About to pass 65536 tokens; iteration = 0
[C66xx_8] Single write test passed
About to pass 65536 tokens; iteration = 0
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Link Speed is 4 * 1.25G Gbps
[C66xx_8] Link Speed is 4 * 1.25G Gbps
[C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 16131 Mcycles
[C66xx_8] Passed 65536 tokens round trip (read+write through hyplnk) in 16131 Mcycles
[C66xx_0] Approximately 246146 cycles per round-trip
[C66xx_8] Approximately 246146 cycles per round-trip
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Checking statistics
[C66xx_8] Checking statistics
[C66xx_0] About to pass 65536 tokens; iteration = 1
[C66xx_8] About to pass 65536 tokens; iteration = 1
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Link Speed is 4 * 1.25G Gbps
[C66xx_8] Link Speed is 4 * 1.25G Gbps
[C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 16131 Mcycles
[C66xx_8] Passed 65536 tokens round trip (read+write through hyplnk) in 16131 Mcycles
[C66xx_0] Approximately 246148 cycles per round-trip
[C66xx_8] Approximately 246148 cycles per round-trip
[C66xx_0] === this is not an optimized example ===
[C66xx_8] === this is not an optimized example ===
[C66xx_0] Checking statistics
[C66xx_8] Checking statistics
[C66xx_0] About to pass 65536 tokens; iteration = 2
[C66xx_8] About to pass 65536 tokens; iteration = 2
Perhaps for hardware problems I can not get to 10Gbps in 4x...
Ok using a slower speed (3.125) even my original project is working pretty good, apart from some doubt still to be resolved (it seems that the DSPs are not able to transmit data to each other simultaneously).
Probably is just an hardware problem that kept me from using the higher speeds.
