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TMS320C6748 Power Consumption

Tony Kunkel
Prodigy 190 points
Other Parts Discussed in Thread: TMS320C6748

Hello,

I've recently been having an issue with excessive current draw from the TMS320C6748 DSP. In some cases, the device will power up correctly and the total current draw for the system is 1.55 A. However, it will also power up in a different state, where the current draw for the system is 2.35 A. I have checked the current draw on different rails and it is clear that the 3.3 V supply is drawing the excess current. The device has operated as expected in the past in both states, so I was wondering if there could be a configuration issue with the DSP or if it is more likely that the chip has been compromised. I have also noticed that in recent testing the output voltage on the 3.3 V line is being pulled low (to ~2.98 V) and the 1.8 V connected to the DSP is being pulled high (~2.6 V). While this is happening, the DSP is no longer operating correctly. The initial design did not have a power monitor circuit to hold the DSP in RESET until power was good on all 3 rails, so that has been implemented more recently, but the same behavior persists. Is there something that I'm missing that would cause a soft short between these rails? Also, what happens to the DSP if a FPGA tries to send data across while it is in RESET (this shouldn't be happening, but I'm curious as to the result)?

Thanks

  • 0
    TI__Guru* 84110 points

    Tony,

    Is this on your own board or an EVM or DSK or other eval board?

    You will need to do more narrowing of this problem. It is unlikely that this is a "soft short", if by that you mean a software-created problem. There could be some peripheral that is driving opposed to some other device on the board, for example, but that can only be determined by your continued debug.

    It is very hard to track down problems like this, and it usually requires cutting traces or lifting pads to isolate different parts of the power planes.

    If there is something in the software procedure that is enabling this, isolating that will also help.

    The very heavy load may be able to be isolated using IR imaging, if that is available to you. The point of the extra currect draw will certainly become hotter.

    Tony Kunkel said:
    what happens to the DSP if a FPGA tries to send data across while it is in RESET (this shouldn't be happening, but I'm curious as to the result)?

    You are asking about something that is not happening at a time when nothing can be happening, and want to know what would then happen? If the DSP is in RESET, it will not respond to anything. You can check the datasheet to see what state particular I/Os are in when RESET is active, for the pins to which the FPGA is connected. Then you will know exactly what the "reaction" will be.

    Regards,
    RandyP