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DM8168 capture 4 ch 1080p@30

colin he1
Intellectual 665 points
Other Parts Discussed in Thread: TVP5147

Hi, our application is DM8168 capture 4 ch 1080p@30 from FPGA, but we are not sure that FPGA how to output 4 ch 1080p@30 video data. Is there some reference document description about DM8168 capture 4 ch 1080p@30 in detail? thanks.

  • 0
    TI__Guru**** 475745 points

    it should be possible. use bt656 style of embedded sync code and vip will be able to capture 4 1080p30 streams

    0xFF 0x00 0x00 0xXY

     

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 665 points

    Thanks for your reply. 

    DM8168 has two video input port. Every port has 2 clock signal(CLK_A, CLK_B), VIN[0]A_CLK, VIN[0]B_CLK, VIN[1]A_CLK, VIN[1]B_CLK. In this usecase(capture 4 channel 1080p@30), I am not sure that the only VIN[0]A_CLK,VIN[1]A_CLK  or the all of them are used for the clock signal?

  • 0 in reply to colin he1
    TI__Guru**** 475745 points

    Since you have four independent input streams, you need to connect pixel clock to all of these pins..

     

    Rgds,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 665 points

     

    Because that our board only use VIN[0]A_CLK, VIN[1]A_CLK signal, and VIN[0]B_CLK,VIN[1]B_CLK not used. And VIN[0], VIN[1] use Y/C 16bit.

    Can  we  use the only VIN[0]A_CLK,VIN[1]A_CLK  signal, VIN[0]A_CLK for channel 0 and channel 1,   VIN[1]A_CLK for channnel 2,channel 3?

    We are not sure that  DM1868 captures 4 channel 1080p@30 video sequence diagram. Is there some documents descript about this?  so our FPGA engineer know to how output 4 channel 1080p@30 to DM8168 via this sequence diagram.

  • 0 in reply to colin he1
    Genius 3700 points

    Hi Coling he1,

         I think that if you need to use 4 input ports, you need to put a clock in every clock pin for each port

    VIN[0]A_CLK -> /dev/video0 → Capture VIP 0 Port A
VIN[0]B_CLK -> /dev/video4 → Capture VIP 0 Port B
VIN[1]A_CLK -> /dev/video5 → Capture VIP 1 Port A
VIN[1]B_CLK -> /dev/video6 → Capture VIP 1 Port B

       If you don't do this the VPSS wouldn't be able to get frames, you can see that we had to solder a wire in the DM8168-EVM for the same reason in order to make the TVP5147 work, since originally it didn't have the clock connected to VIN[1]B_CLK otherwise the VPSS wouldn't get frames

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/326172/1170437.aspx#1170437

       Also if you are capturing different video streams you can't share the clock. If you want 4 inputs you need to configure the 4 video input ports in 8bits and set a clock for each one.