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config DSP cache for DM8148

Wade Xu
Intellectual 350 points

Other Parts Discussed in Thread: SYSBIOS

What is the right way to configure a memory space (for example at bf000000) to be none-cache (when assessed by C674x DSP core)?

I tried to add MAR bit in *.cfg file, for example:

Var Cache       = xdc.useModule('xdc.runtime.knl.Cache');
/* Disable caching for remote logging area, which start from 0xbf000000 */
Cache.MAR191_192 = 0x00000000;

The build process give error of (no element named 'MAR191_192')

Thanks.

  • 0
    TI__Expert 6860 points

    The Cache setting on the DSP cannot be set on an MAR bit by Mar bit basis.  You have the set the entire MAR register corresponding to the address range you want to make cacheable .

     

    Here is an example of how you would set a particular MAR register in your DSP configuration.

     

    ------------------------------------

    /*  configure external memory cache property

    *

    *  8000_0000 - 9FFF_FFFF  2000_0000  ( 512 MB) Cache.MAR128_159

    *  ----------------------------------------------------------------------------

    *  8000_0000 - 8DFF_FFFF   E00_0000  ( 224 MB) --------    don't care

    *  8E00_0000 - 8E02_FFFF     3_0000  ( 192 KB) SR_0, SR_1  no-cache      MAR142

    *  8E02_0000 - 8EFF_FFFF    FD_0000  ( ~15 MB) --------    no-cache      MAR142

    *  8F00_0000 - 8FBF_FFFF    C0_0000  (  12 MB) DSP_PROG    cache enable  MAR143

    *  8FC0_0000 - 8FFF_FFFF    40_0000  (   4 MB) --------    cache enable  MAR143

    *  9000_0000 - 9FFF_FFFF  1000_0000  ( 256 MB) --------    don't care

    */

    Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');

    Cache.MAR128_159 = 0x00008000;  /* xxxx xxxx xxxx xxxx 10xx xxxx xxxx xxxx */

    ------------------------------------

     

    The below is taken from the SysBios  6.x API documentation:

    MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF) 

    DETAILS

    If undefined by the user, this parameter is configured to match the memory map of the platform. Each memory region defined in the platform will have all of its corresponding MAR bits set.

    To override the default behavior you must initialize this parameter in your configuration script:

      // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF

      Cache.MAR0_31 = 0x00000000;

    MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)

    MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)

    MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)

    MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)

    MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)

    MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)

    MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)

  • 0 in reply to Arnie Reynoso
    Intellectual 350 points

    Thank you for the detail example. Problem is solved.