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PCIe Device Tree Bindings

Bill
Intellectual 645 points

I am using the PCI-Keystone driver on my device and cannot figure out how to properly configure the device tree binding.

When I open up the Y:\personal_folders\william\devel_tools\linux\Documentation\devicetree\bindings\pci\pci-keystone.txt file, I get basic information on the binding but it does not get specific on what the ranges tag means. I am trying to read and write to an FPGA which has already been properly enumerated at boot.

I am currently assuming that after device enumeration I should have the ability read/write to the FPGA registers through the PCIe_data registers located @ 0x5000_0000 which should get mapped to the FPGA using the configuration in the device tree.

Here is the output during Linux Boot:

[ 2375.747593] keystone-pcie: keystone_pcie_rc_init - start
[ 2375.747663] keystone2_pcie_serdes_setup
[ 2375.749360] keystone2_pcie_serdes_setup done, en_link_train = 1
[ 2375.749386] keystone-pcie: MEM 0x0000000050000000..0x000000005fffffff -> 0x00
00000050000000
[ 2375.749394] keystone-pcie: IO 0x0000000024000000..0x0000000024003fff -> 0x000
0000000000000
[ 2375.749422] keystone-pcie: pcie - number of legacy irqs = 4
[ 2375.749464] keystone-pcie: pcie - number of MSI host irqs = 8, msi_irqs = 32
[ 2375.836005] keystone-pcie: Doing PCI Setup...Done
[ 2375.836010] keystone-pcie: Starting PCI scan...
[ 2375.836103] PCI host bridge to bus 0000:00
[ 2375.836113] pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff]
[ 2375.836119] pci_bus 0000:00: root bus resource [io  0x0000-0x3fff]
[ 2375.836125] pci_bus 0000:00: No busn resource found for root bus, will use [b
us 00-ff]
[ 2375.836318] PCI: bus0: Fast back to back transfers disabled
[ 2375.836325] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), rec
onfiguring
[ 2375.836670] PCI: bus1: Fast back to back transfers disabled
[ 2375.836693] keystone-pcie: Ending PCI scan...
[ 2375.836700] keystone-pcie: keystone_pcie_map_irq: slot 0, pin 1
[ 2375.836704] keystone-pcie: keystone_pcie_map_irq: legacy_irq 572
[ 2375.836710] keystone-pcie: keystone_pcie_map_irq: slot 0, pin 1
[ 2375.836713] keystone-pcie: keystone_pcie_map_irq: legacy_irq 572
[ 2375.836730] pci 0000:00:00.0: BAR 8: assigned [mem 0x50000000-0x501fffff]
[ 2375.836737] pci 0000:00:00.0: BAR 9: assigned [mem 0x50200000-0x503fffff pref
]
[ 2375.836743] pci 0000:00:00.0: BAR 7: assigned [io  0x1000-0x1fff]
[ 2375.836750] pci 0000:01:00.0: BAR 0: assigned [mem 0x50000000-0x500fffff]
[ 2375.836759] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 2375.836764] pci 0000:00:00.0:   bridge window [io  0x1000-0x1fff]
[ 2375.836771] pci 0000:00:00.0:   bridge window [mem 0x50000000-0x501fffff]
[ 2375.836778] pci 0000:00:00.0:   bridge window [mem 0x50200000-0x503fffff pref
]
[ 2375.836787] PCI: enabling device 0000:00:00.0 (0140 -> 0143)
[ 2375.836792] keystone-pcie: keystone_pcie_rc_init - end

I am sorry for the lack of detail for my problem but I have never dealt with PCIe before and am having trouble understanding the configurations steps.

  • 0
    TI__Guru* 81335 points

    Hi Bill,

    Please provide below information to help you.

    1. What is your Keystone II device Part number?

    2. Are you working on custom board or EVM?

    3. Are you able to see the PCI device from Linux prompt using "lspci" command?

    4. How the FPGA is accessed from Linux? Are you running kernel driver or User space driver to access FPGA registers?

    The Keystone PCIe driver will help you to enumerate and configure the configuration space registers of PCIe. From my understanding, you will need to implement PCI device specific driver to access the FPGA. Please provide of logs for the steps followed to read/write FPGA registers.

    Thanks for the post.

  • 0 in reply to Raja
    Intellectual 645 points

    My Keystone EVM is the EVMK2K.

    When I run the lspci command I am able to see both my FPGA board and "PCI bridge: Texas Instruments Device 888 (rev 01)"

    I was under the impression from the limited documentation out there on the PCI driver, that once the Driver enumerates the device, all I should have to do is write to PCI_data memory space located at 0x50000000. I thought that when I write to that address, the PCI interface will uses that outbound address translation to come up with a PCI address and then write that data to the PCI interface. In test all I have done was $devmem2 0x50000000 w 0x5 to test this theory. After that I was stuck because there is nothing discussing the driver online. Is this a valid assumption? Do I need to edit my device tree at all?

  • 0 in reply to Bill
    TI__Guru* 81335 points

    Hi Bill,

    TCI66K2K are supported directly through Local Field Applications Engineers (FAEs.)  These devices are not supported on the E2E forum.  Please contact your local FAE for support of these devices.  If you are not sure who your local FAE is, then please contact your local technical sales representative and they will be able to put you in contact with your local FAE.

    Thanks.

  • 0 in reply to Raja
    Intellectual 645 points

    My AFE has suggested that I continue to use the forums for faster response time. Also, this is not a device specific question. I am looking for documentation on the pcie-keystone driver which should abstract me away from the specifics of the device.

  • 0 in reply to Bill
    TI__Guru* 81335 points

    Hi Bill,

    Fine. I will review the documents and post my suggestions. Thank you for patience.

  • 0 in reply to Raja
    Intellectual 470 points

    Hi,

    I have resolved my problem, but it leaves one more question to go along with it.

    Origianlly my lspci -v output would be:

    lspci -v
    00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal d
    ecode])
            Flags: bus master, fast devsel, latency 0
            Memory at <ignored> (32-bit, non-prefetchable)
            Memory at <ignored> (32-bit, prefetchable)
            Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
            I/O behind bridge: 00001000-00001fff
            Memory behind bridge: 50000000-501fffff
            Prefetchable memory behind bridge: 50200000-503fffff
            Capabilities: [40] Power Management version 3
            Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
            Capabilities: [70] Express Root Port (Slot-), MSI 00
            Capabilities: [100] Advanced Error Reporting

    01:00.0 Memory controller: Device 1708:7022
            Subsystem: Xilinx Corporation Device 0007
            Flags: fast devsel, IRQ 572
            Memory at 50000000 (32-bit, non-prefetchable) [disabled] [size=1M]
            Capabilities: [80] Power Management version 3
            Capabilities: [90] MSI: Enable- Count=1/4 Maskable- 64bit+
            Capabilities: [c0] Express Endpoint, MSI 00
            Capabilities: [100] Advanced Error Reporting

    This shows that memory at 50000000 is disabled. By using this command

    $setpci-s 01:00.0 COMMAND=02

    I am able to enable the memory region and then the read and writes are able to be seen on the FPGA. what causes this to be disabled at boot? Is this something going on in my FPGA build or is it something that can be enabled automatically from the ARM?

    Thanks again for all of your help

  • 0 in reply to William H
    TI__Guru* 81335 points

    Hi William,

    Sorry for the delayed response.

    William: said:

    I am able to enable the memory region and then the read and writes are able to be seen on the FPGA. what causes this to be disabled at boot? Is this something going on in my FPGA build or is it something that can be enabled automatically from the ARM?

    From the above post, I understand that "setpci" does the configuration of PCIe device on the bus and it should be an expected behavior. It is specific to ARM and not with FPGA.

    Let us assume, We have more than 4 PCIe devices connected on the PCIe bus. The PCIe host driver will enumerate the PCIe devices on the bus and allocate the memory and IO regions. The PCIe device specific driver/application is required to enable and use the PCIe device features.

    Thanks.