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DMC exception raised on PCIe outbound read at 0x60000000

Hawk Chan
Prodigy 230 points
Other Parts Discussed in Thread: TMS320C6657, SYSBIOS

Hi,

    I am using TMS320C6657 as an PCIe endpoint.

    I configured the OB_OFFSET(0) register to remap local memory address 0x60000000 to PCIe address in RC (e.g. 0xdd000000). And I tried to write something to RC and succeeded, however, when I tried to read the data back, a DMC exception was raised and SYS/BIOS printed the following for me:

A0=0x80951ec0 A1=0x8
A2=0x0 A3=0x84555120
A4=0xf A5=0x80809541
A6=0x35363738 A7=0x31323334
A8=0x1 A9=0x84571464
A10=0x0 A11=0x0
A12=0x0 A13=0x0
A14=0x0 A15=0x0
A16=0x80951d48 A17=0x30
A18=0x80951d48 A19=0x0
A20=0x0 A21=0x0
A22=0x471d75ce A23=0xdbd6b7fe
A24=0x679c2372 A25=0x2200
A26=0x18480b30 A27=0x263bffbf
A28=0xfeedd8b7 A29=0x4000
A30=0x1 A31=0x200
B0=0x80951f40 B1=0x84544404
B2=0x0 B3=0x8455b470
B4=0x20c B5=0x8456bb41
B6=0x0 B7=0x0
B8=0x0 B9=0x0
B10=0x80951fc8 B11=0x0
B12=0x0 B13=0x0
B14=0x84572fc0 B15=0x80951eb0
B16=0x30 B17=0x80951f74
B18=0x8456bb39 B19=0x845714ac
B20=0x12893162 B21=0x1
B22=0x20d B23=0x0
B24=0x845714b0 B25=0x5bfdcfef
B26=0xfd4f02cd B27=0x7b6b9ff2
B28=0x2810 B29=0x2810
B30=0x80851344 B31=0xffffffff
NTSR=0x1020c
ITSR=0x20d
IRP=0x84544404
SSR=0x0
AMR=0x0
RILC=0x0
ILC=0x0
Exception at 0x84555124
EFR=0x40000000 NRP=0x84555124
DMC Exception MPFAR=0x6f001000 MPFSR=0x120
Supervisor Read violation, Fault ID=0x1
ti.sysbios.family.c64p.Exception: line 255: E_exceptionMin: pc = 0x84555124, sp = 0x80951eb0.
To see more exception detail, use ROV or set 'ti.sysbios.family.c64p.Exception.enablePrint = true;' 

Note that I didn't use EDMA to read or write, so the bus master is CPU itself. It seems that I haven't got enough priviledge for the CPU to access 0x60000000~0x6FFFFFFF just for reading (writing is OK and is behaving as I expected). So I added the following code in my startup code to configure the XMC module (similar to the GEL code):

#define XMC_BASE_ADDR (0x08000000)
#define XMPAX2_L     (*(volatile unsigned int*)(XMC_BASE_ADDR + 0x00000010))
#define XMPAX2_H     (*(volatile unsigned int*)(XMC_BASE_ADDR + 0x00000014))
#define XMPAX4_L     (*(volatile unsigned int*)(XMC_BASE_ADDR + 0x00000020))
#define XMPAX4_H     (*(volatile unsigned int*)(XMC_BASE_ADDR + 0x00000024))

XMPAX4_L = 0x60000036;    // PCIe data space
XMPAX4_H = 0x6000001B;    // 256MB

The DMC exception is gone this time, however, the PCIe outbound write at  0x60000000 would not take effect any more, and I find that I can always read the data back with the value I wrote in, even if I configure the OB_OFFSET register to an invalid PCIe address. Is cache involved into this issue?

To be honest, I don't understand the architechure of the XMC module, especially the address remapping and the relationship with L1,L2 cache. Could anyone expain to me how I should configure the XMC to get access to the PCIe data space and perform an outbound read correctly? Thanks a lot!

Regards,

Hawk

  • 0
    Prodigy 230 points

    Hi,

        I am using EVMC6657+T MDXEVMPCI on a linux PC.

        I managed to configure the BARs and ObOFFSETn to perform an outbound write correctly. This is verified by a simple write to PCIe data space (redirected to physical memory on PC) and the pattern written can be read from PC successfully.

        However, I get an DMC exception once I start an outbound read, and SYS/BIOS will print exception messages in the handler of NMI. The message is as follows:

        http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/343434.aspx

        I also tried outbound read with EDMA, no DMC exception is raised (EDMA error interrupt is disabled), however, the data read back is always zero.

        Is it a previledge issue? Did the SYS/BIOS configure the MPU when it started?  I am confused and I've been stuck at here for several days. Hoping that anyone can help me, thanks!

        Regards,

        Hawk

  • 0 in reply to Hawk Chan
    TI__Guru* 81335 points

    Hi Hawk,

    I apologize for not getting back to you earlier on this. Please check below thread which may help you. 

    http://e2e.ti.com/support/embedded/tirtos/f/355/p/311275/1083378.aspx

    From my understanding, It looks like SYS/BIOS question. Could you please post it in RTOS forum? 

    Thanks.

  • 0 in reply to Raja
    Prodigy 230 points

    Hi Rajasekaran,

    Thanks for your reply. I'm not trapped by this issue currently because EDMA is working correctly instead of a direct CPU-read. I'll post it to the RTOS forum if I need further help. Thanks.