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AM3354 eQEP Edge Capture Unit UPEVNT

Weiren Tee
Expert 1100 points

Hi,

Does anyone knows are there any other event(s) beside the UPEVNT that can cause the capture timer (QCTMR) value to be latched into the capture period register (QCPRD)?

Below is an extract from the AM335x ARM® Cortex™-A8 Microprocessors (MPUs) technical reference manual ,Page 2164

The eQEP capture timer (QCTMR) runs from prescaled SYSCLKOUT and the prescaler is programmed
by the QCAPCTL[CCPS] bits. The capture timer (QCTMR) value is latched into the capture period register
(QCPRD) on every unit position event and then the capture timer is reset, a flag is set in
QEPSTS[UPEVNT] to indicate that new value is latched into the QCPRD register. Software can check this
status flag before reading the period register for low speed measurement and clear the flag by writing 1. 

Thank you in advance :)

Regards,

Weiren

  • 0
    TI__Guru**** 393215 points

    I don't think there are any other possibilities, but there are additional latches:

    Capture Timer (QCTMR) and Capture period register (QCPRD) can be configured to latch on following
    events.
    • CPU read of QPOSCNT register
    • Unit time-out event
    If the QEPCTL[QCLM] bit is cleared, then the capture timer and capture period values are latched into the
    QCTMRLAT and QCPRDLAT registers, respectively, when the CPU reads the position counter
    (QPOSCNT).
    If the QEPCTL[QCLM] bit is set, then the position counter, capture timer, and capture period values are
    latched into the QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out.

  • 0 in reply to Biser Gatchev-XID
    Expert 1100 points

    Hi Biser,

    Thanks for your reply.

    Those additional latching will not modify the Capture Timer (QCTMR) and Capture period register (QCPRD) registers right? They will only latch the values to other registers from what I understood.

    Regards,

    Weiren

  • 0 in reply to Weiren Tee
    TI__Guru**** 393215 points

    Yes, this is correct.