• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 2326 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335X can not boot MLO(SPL)

shishu yang
Prodigy 180 points
Other Parts Discussed in Thread: AM3359, AM3352

Hello,

I design a custom board as start-kit board,i change AM3359 to AM3352ZCZ60 ,the software version is SDK6.0(i have removed EEPROM support).I boot from UART0 ,and it prints 'C' well,then i transmit MLO with XMODEM in 1K mode finish ,it prints nothing on the teminal any more,MLO can not run.As i know,the MLO functions is initial the DDR and load the uboot,it run in the AM335X inner RAM.I have check the hardware.all votages is ok.i have try boot from SD card,but  it does not work too!

What i miss?Should i modify any other u-boot code between AM3359 and AM3352? 

  • 0
    Prodigy 180 points

    I can boot from SD card now ,but it stop at "CONFIG_SPL_BUILD IS DEFINE rtc32k_enable",the full boot message is like this:

    CCCCCCCC
    U-Boot SPL 2013.01.01 (Mar 04 2014 - 10:19:03)
    CONFIG_SPL_BUILD IS DEFINE rtc32k_enable

    I have a 32.768kHz crystal on the board,why it stop at here?

  • 0 in reply to shishu yang
    Prodigy 180 points

    I change the DDR3 configurations in ddr_defs.h ,my DDR3 is 1333MHZ,not the 1600MHz,now it works well:

    /*ddr3-1600  Micron MT41J128M16JT-125 */
    /*#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
    #define MT41J128MJT125_EMIF_TIM1 0x0888A39B
    #define MT41J128MJT125_EMIF_TIM2 0x26337FDA
    #define MT41J128MJT125_EMIF_TIM3 0x501F830F
    #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
    #define MT41J128MJT125_EMIF_SDREF 0x0000093B
    #define MT41J128MJT125_ZQ_CFG 0x50074BE4
    #define MT41J128MJT125_DLL_LOCK_DIFF 0x1
    #define MT41J128MJT125_RATIO 0x40
    #define MT41J128MJT125_INVERT_CLKOUT 0x1
    #define MT41J128MJT125_RD_DQS 0x3B
    #define MT41J128MJT125_WR_DQS 0x85
    #define MT41J128MJT125_PHY_WR_DATA 0xC1
    #define MT41J128MJT125_PHY_FIFO_WE 0x100
    #define MT41J128MJT125_IOCTRL_VALUE 0x18B
    */

    //DDR3-1333
    #define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
    #define MT41J128MJT125_EMIF_TIM1 0x0888A39B
    #define MT41J128MJT125_EMIF_TIM2 0x26337FDA
    #define MT41J128MJT125_EMIF_TIM3 0x501F830F
    #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
    #define MT41J128MJT125_EMIF_SDREF 0x0000093B
    #define MT41J128MJT125_ZQ_CFG 0x50074BE4
    #define MT41J128MJT125_DLL_LOCK_DIFF 0x1
    #define MT41J128MJT125_RATIO 0x30
    #define MT41J128MJT125_INVERT_CLKOUT 0x1
    #define MT41J128MJT125_RD_DQS 0x30
    #define MT41J128MJT125_WR_DQS 0x40
    #define MT41J128MJT125_PHY_WR_DATA 0x70
    #define MT41J128MJT125_PHY_FIFO_WE 0x120
    #define MT41J128MJT125_IOCTRL_VALUE 0x18B

  • 0 in reply to shishu yang
    TI__Guru**** 393215 points

    Thanks for sharing your results on the forum.