Hi,
I setup my system as follows:
- A Microchip serial communication (SPI) transmitter is connected to receivers of McBSP0, McBSP1 and McASP1 ports (on TMS320C6713b) in parallel;
- The transmitter sends 3 x 16-bit halfwords, back-to-back, to the three receivers simultaneously;
- Each halfword starts with a 1-bit frame sync, and data is sent with a 1-bit delay;
- The clock is 6.66MHz.
- The 3 x 16-bit halfwords set is sent repeatedly, at 120us interval.
- I saw on the scope the signal stream for sending each halfword is made with 17 clocks. The three active-high frame sync pulses are on 17-clock-cycles interval;
- The McBSP0, McBSP1, McASP1 ports are all setup for burst mode, and to interrupt after receiving each halfword;
- The three separate receive-data interrupt service routines (isr) each counts the number of halfwords it received, and resets its own counter after receiving 3 halfwords.
Problem:
= I kept finding the three data counters going out of step with each other!
= I made the three isr's each check its own RSYNCERR bit upon receiving a halfword, and output a different pulse pattern on the GP8 pin for visualization
= I found McASP1 declares a RSYNCERR error after receiving every halfword, even after the very FIRST halfword!
= Anybody know what might be wrong?????
= My relevant register setups are as follows:
*McASP1GBLCTL = 0x00000000; // Reset McASP1 to all default values
*McASP1PDEMU = 0x00000000; // Leave serial port clock to run freely during emulation halt
*McASP1RMASK = 0x0000ffff; // Pass 16 received bits only to the CPU
*McASP1RFMT = 0x00018070; // Set for 16-bit (MSB first) data receive, from "Data Port", with 1-bit delay
*McASP1AFSRCTL = 0x00000000; // Set receive frame sync to be from external device
*McASP1ACLKRCTL = 0x00000000; // Set receive clock to be sourced by external device
*McASP1AHCLKRCTL= 0x00008000; // Set receive high-freq clock for internal-sourced operation
*McASP1RTDM = 0x00000001; // Activate only the receive time slot 0 for data reception
*McASP1RINTCTL = 0x00000020; // Enable CPU interrupt when a halfword has been received
// Serializer registers
*McASP1SRCTL0 = 0x00000002; // Set up AXR1[0] to serve as data receive input pin for serial communication
// Global registers
*McASP1PFUNC = 0x00000000; // Set up A-prefixed pins to function for a McASP
*McASP1PDIR = 0x1e000002; // Set up A-prefixed pins to serve as a serial communication port
*McASP1DITCTL = 0x00000000; // Disable the DIT mode
*McASP1DLBCTL = 0x00000000; // Disable the Digital Loop Back mode since not used (not an audio device!)
*McASP1AMUTE = 0x00000181; // Set AMUTE1 to go high when FSR or FSX error occurs
// Start the high-frequency serial clocks
*McASP1GBLCTL |= 0x00000202; // Start the AHCLKX and AHCLKR clocks
*McASP1RSTAT = 0x000000f7; // Clear the receive status register (by writing '1's to these bits!!!)
*McASP1GBLCTL |= 0x00000404; // Start the serializers
while ((*McASP1GBLCTL & 0x00000404) != 0x00000404) {};
*McASP1GBLCTL |= 0x00000808; // Start the McASP1 receive and transmit state machines
while ((*McASP1GBLCTL & 0x00000808) != 0x00000808) {};
*McASP1GBLCTL |= 0x00001010; // Start the McASP1 frame sync generators
while ((*McASP1GBLCTL & 0x00001010) != 0x00001010) {};
Any help would be much much appreciated. This development has gone overtime for way too long already!
C.M.
