• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 351 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

qmssIpcBenchmark project

cherish
Intellectual 870 points

hi

in the project  qmssIpcBenchmark

System_printf ("Core %d : L1D cache size %d. L2 cache size %d.\n", coreNum, CACHE_getL1DSize(), CACHE_getL2Size());

System_printf ("address of monolithicDesc[] = 0x%x. Converted=0x%x\n", monolithicDesc, l2_global_address ((UInt32) monolithicDesc));

the log is：

Core 0 : L1D cache size 4. L2 cache size 0.

address of monolithicDesc[] = 0xc100000. Converted=0x1c100000

1.i want to know the log：cache size 4，what is its meaning？

2.the address of   monolithicDesc[] = 0xc100000 ，it is in the shared memory，why it is mapped to 0x1c100000，the address is a reserved in 6678 memory map.

  • 0
    TI__Mastermind 20790 points

    Cherish,

    Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to zero.       For example, address location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory.

    Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular core should always use the global address only.

    Multicore Shared Memory(MSM):
    Logical 32-bit address are                                   0C000000 - 0C3FFFFF
    Its equivalent Physical 36-bit address are     0 0C000000 - 0 0C3FFFFF

    I could not find the address  0x1c100000, refer the below snapshot from datasheet.

    CACHE_getL1DSize, This function is used to get the L1 Data Cache Size like Configured 4K Cache Size
    CACHE_getL2Size, This function is used to get the L2 cache size.
    Find more detailed information for cache at the TMS320C66x DSP Cache User Guide,
    http://www.ti.com/lit/sprugy8

  • 0 in reply to Pubesh
    Intellectual 870 points

    thanks for your reply.

    but the log in CCS console:  i just use example ,run it.

    address of monolithicDesc[] = 0xc100000. Converted=0x1c100000

    as above saied,0xc100000 is in Sharedmem,but the l2_global_address of it is in a reseved memory section.

    the Sharedmem can be accessed by all cores origianal,why it should be mapped. i just can not understand.

    some Variables in the Local L2 should be mapped to l2_global_address of own core.for example,0x00800 0000 should mapped to 0x1080 0000 of core0 L2.

     

    and:the CCS log: L1D cache is 4k;but in the platform :ti.platform.c6678l in the xdctool package,the cache assigned is :L1P 32KB ;L1D 32KB.

    why?

  • 0 in reply to cherish
    TI__Mastermind 20790 points

    Cherish,

    I will make the setup and test the same project. Mean time find more detailed information for cache and memory related at the device datasheet, cache user guide.