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AM3505 use JLink debug in sdram

chars ant
Prodigy 50 points
Other Parts Discussed in Thread: AM3505

Hi,All

I have a custom board.Cpu is TI's AM3505, and NT5TU64M16GG-3C ddr2 (SDRAM). cpu run normal.When debug in SRAM with x-load, evrything is ok. Normal output appears on the uart1.But when I want to debug in SDRAM ,some problems happend .

Jlink gdb code print:

Reading all registers
WARNING: Failed to read memory @ address 0x00000000
Read 4 bytes @ address 0x00000000 (Data = 0xAAAAAAAA)
Read 4 bytes @ address 0xFFFFFFFC (Data = 0xFFFFFFFF)
WARNING: Failed to read memory @ address 0x00000000
Read 4 bytes @ address 0x00000000 (Data = 0xAAAAAAAA)
Read 4 bytes @ address 0xFFFFFFFC (Data = 0xFFFFFFFF)
WARNING: Failed to read memory @ address 0x00000000
Read 4 bytes @ address 0x00000000 (Data = 0xAAAAAAAA)
WARNING: Failed to read memory @ address 0x00000000
Read 4 bytes @ address 0x00000000 (Data = 0xAAAAAAAA)
WARNING: Failed to read memory @ address 0x00000000
Read 4 bytes @ address 0x00000000 (Data = 0xAAAAAAAA)
Target interface speed set to 30 kHz
Target endianess set to "little endian"
Resetting target
Writing 0x00000020 @ address 0x48004C10
Writing 0x00000020 @ address 0x48004C00
Sleep 10ms
Writing 0x0000AAAA @ address 0x48314048
Sleep 10ms
Writing 0x00005555 @ address 0x48314048
Writing 0x00000003 @ address 0x48306D40
Target interface speed set to 1000 kHz
Writing 0x00110011 @ address 0x48004D00
Sleep 10ms
Writing 0x0000032A @ address 0x48004A40
Writing 0x094C1900 @ address 0x48004D40
Writing 0x00006019 @ address 0x48004D44
Writing 0x00000002 @ address 0x48004D48
Writing 0x00370037 @ address 0x48004D00
Sleep 100ms
Writing 0x00000015 @ address 0x48004904
Sleep 10ms
Writing 0x00000001 @ address 0x48004944
Writing 0x0010FA0C @ address 0x48004940
Writing 0x00000077 @ address 0x48004904
Sleep 100ms
GDB closed TCP/IP connection
Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x00014000 (Data = 0xEA000232)
WARNING: Failed to read memory @ address 0x00013FFC
Read 4 bytes @ address 0x00013FFC (Data = 0xAAAAAAAA)
Read 4 bytes @ address 0x00014000 (Data = 0xEA000232)
WARNING: Failed to read memory @ address 0x00013FFC
Read 4 bytes @ address 0x00013FFC (Data = 0xAAAAAAAA)
Read 4 bytes @ address 0x00014000 (Data = 0xEA000232)
Read 4 bytes @ address 0x00014000 (Data = 0xEA000232)
Read 4 bytes @ address 0x00014000 (Data = 0xEA000232)
Target interface speed set to 30 kHz
Target endianess set to "little endian"
Resetting target
Writing 0x00000020 @ address 0x48004C10
Writing 0x00000020 @ address 0x48004C00
Sleep 10ms
Writing 0x0000AAAA @ address 0x48314048
Sleep 10ms
Writing 0x00005555 @ address 0x48314048
Writing 0x00000003 @ address 0x48306D40
Target interface speed set to 1000 kHz
Writing 0x00110011 @ address 0x48004D00
Sleep 10ms
Writing 0x0000032A @ address 0x48004A40
Writing 0x094C1900 @ address 0x48004D40
Writing 0x00006019 @ address 0x48004D44
Writing 0x00000002 @ address 0x48004D48
Writing 0x00370037 @ address 0x48004D00
Sleep 100ms
Writing 0x00000015 @ address 0x48004904
Sleep 10ms
Writing 0x00000001 @ address 0x48004944
Writing 0x0010FA0C @ address 0x48004940
Writing 0x00000077 @ address 0x48004904
Sleep 100ms
Writing 0x00000000 @ address 0x48002264
Writing 0x00000006 @ address 0x6D0000E4
Writing 0x00000006 @ address 0x6D0000E8
Writing 0x00000000 @ address 0x6D0000EC
Writing 0x00002411 @ address 0x6D000060
Sleep 20ms
WARNING: Failed to read memory @ address 0x00000000
Read 4 bytes @ address 0x00000000 (Data = 0xAAAAAAAA)
Read 4 bytes @ address 0x002006A8 (Data = 0x00550054)
Read 4 bytes @ address 0x002006A4 (Data = 0x00530052)
Read 4 bytes @ address 0x002006A8 (Data = 0x00550054)
Read 4 bytes @ address 0x002006A4 (Data = 0x00530052)
Read 4 bytes @ address 0x002006A8 (Data = 0x00550054)
Read 4 bytes @ address 0x002006A8 (Data = 0x00550054)
Read 4 bytes @ address 0x002006A8 (Data = 0x00550054)
WARNING: Failed to read memory @ address 0x00000000
Read 4 bytes @ address 0x00000000 (Data = 0xAAAAAAAA)
Writing 0x04446248 @ address 0x6D000018
Writing 0x04446248 @ address 0x6D00001C
Writing 0x141631CA @ address 0x6D000020
Writing 0x141631CA @ address 0x6D000024
Writing 0x00000157 @ address 0x6D000028
Writing 0x00000157 @ address 0x6D00002C
Writing 0x80000000 @ address 0x6D000038
Writing 0x80000000 @ address 0x6D00003C
Writing 0x0000050E @ address 0x6D000010
Writing 0x0000050E @ address 0x6D000014
Writing 0x48801632 @ address 0x6D000008
Downloading 6776 bytes @ address 0x80E80000
Downloading 157 bytes @ address 0x80E81A78
Downloading 20 bytes @ address 0x80E81B18
Writing register (PC = 0x80e80000)
Read 4 bytes @ address 0x80E810EC (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E80098 (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E8013C (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E800F4 (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E802BC (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E81084 (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E81008 (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E80050 (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E80050 (Data = 0xFFFFFFFF)
Read 4 bytes @ address 0x80E80000 (Data = 0xFFFFFFFF)

Firstly, gdb cann't read cpu register normal.Some strange address appeared.

Secondly, data in SDRAM is invalid.May be some errors in my configuration files.

Next is all code about SDRAM initialize:

minitor writeu32 0x48002584 = 0x00008600

monitor writeu32 0x6D000018 = 0x04446248
monitor writeu32 0x6D00001C = 0x04446248
monitor writeu32 0x6D000020 = 0x141631CA
monitor writeu32 0x6D000024 = 0x141631CA
monitor writeu32 0x6D000028 = 0x157
monitor writeu32 0x6D00002C = 0x157
monitor writeu32 0x6D000038 = 0x80000000
monitor writeu32 0x6D00003C = 0x80000000
monitor writeu32 0x6D000010 = 0x50E
monitor writeu32 0x6D000014 = 0x50E
monitor writeu32 0x6D000008 = 0x48801632

please help me ...

  • 0
    TI__Guru**** 393215 points

    Does the system boot normally without JTAG?

  • 0 in reply to Biser Gatchev-XID
    Prodigy 50 points

    Hi  Biser Gatchev-XID

     Thanks for your reply so fast. To be honest, I don't know whether system boot normally without JTAG. Beacuse I hava not a MMC or correct configured USB port can be use to flash nand, so I hava never programmed my image(x-load.bin) files into nand flash.But the x-load debug in SRAM is normally, so I think can flash image into nand after configuring SDRAM works well. But it's seems too hard.I hope get some seggestion from you . 

  • 0 in reply to Biser Gatchev-XID
    Prodigy 50 points

    Hi Biser(All):

    Now I debug the x-load in SRAM , because it works well. After my ddr configure is completed , I write some code ddr(MY SDRAM) to read /write my ddr at address 0x8000000.For example ,write 0x8000000=0xA5A5A5A5.And then I read the same address after writing . It's 0x80000000=0xA5A5ABD5. The same ddr address ,but the data is not the same data I have writed.I am confused.I think my ddr configuratiion is not corrected configured.Is there some correct configuration AVGs to my SDRAM?

  • 0 in reply to Biser Gatchev-XID
    Prodigy 50 points

    Hi Biser(All),

    I debug my x-load in sram ,the print is normal. And I got a LogicPD EVM board, I think it's hardware have not any problems. So I find out DDR2 datasheet about it. My development environment is Ubuntu+Eclipse+Jlink+GDB+x-load.

    I configure the gdbinit commands about ddr2 with datasheet.When I disable the EMIF4 configuration code in xload, and debug in DDR2.Everything is ok but the printf. There are some unreadable code print from uart on the LogicPD.

    How? The code running well ,I don't know .

    There also are some confuse with DDR2 configuration.

    1.My CPU output 166Mhz clock for DDR2, And my ddr2 speed is 667,CL-TRP-TRCD is 5-5-5. Which tck I should pick? 6ns or 3ns?

    2.When I use the same configuration to debug uboot in DDR2,  It can't running even! So ,is some problem with my ddr2 configuration?

    Best regards!

    From Eathen

  • 0 in reply to chars ant
    TI__Guru**** 393215 points

    chars ant said:
    1.My CPU output 166Mhz clock for DDR2, And my ddr2 speed is 667,CL-TRP-TRCD is 5-5-5. Which tck I should pick? 6ns or 3ns?

    tck should be the real clock at which you are running the memory.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 50 points

    Hi Biser(All):

    There is a qustion  confuse me today. I see the code in xload, and then I find that not all SDRC Pin mux is setted up.

    This take affect on reading and writing on DDR2?

    And I have not found the code about reading and wrrting DDR2 in xload code before I modify the xload code . Except for configuring the EMIF......