Hi all,
I am using XTCIEVMK2X EVM.
Developing environment is: CCS ver 5.4.0.00091; MCSDK Packages: 3_00_01_12
Bootmode: ARM SPI Little Endian mode.
We have been using DDR3 memory as shared memory between Host application (running on ARM core 0) and DSP cores.
We have allocated DDR3 memory from 0xB2380000 to 0xB2390000 as shared region between ARM and DSP core0.
0xB2390000 to 0xB23A0000 as shared region between ARM and DSP core1. Similarly for other cores.
I am using 'mpmcl' commands to load and run DSP cores.
For testing purpose, I have used just two cores.
root@keystone-evm:~# mpmcl load dsp0 sh10_core.out
load succeded
root@keystone-evm:~# mpmcl load dsp1 sh10_core.out
load succeded
root@keystone-evm:~# mpmcl run dsp0
run succeded
root@keystone-evm:~# mpmcl run dsp1
run succeded
On CCS, I have observed that the updated DDR3 shared memory of core 0 (0xB2380000 to 0xB2390000) is getting reset as soon as I give command 'mpmcl run dsp1'
I am not using sys-bios / IPC / OpenMP / OpenCL.
With single core i.e. core 0, we are able to work DDR3 memory as shared region between Host application. No issues with single core and we trying to extend it to other cores.
Can you please provide the reason why the DDR3 shared memory of core 0 is getting reset when I run other core ?
Thanks in advance.
Best regards,
Rajanikanth.
