DM8148 with 2GB DDR3 on board. MCFW compilation failed

Marat Shchuchinsky

3858.dvr_rdk_c6xdsp_debug_2048M_512M.xe674.txtHello TI' teams.

I have developed customer board for DM8148 and 2GB physical memory on board.
As software I use MCFW version 3.5 from ud-works.
My customer board have DM8148 (PG3.0) and 2GB of DDR3 memory.
DDR memory test by Jtag and DDR write leveling both work fine on my board.

MCFW compiled successfully when I use memory configuration file for 512MB supplied by ud-works
Bu, when I tried create new memory configuration file for 2GB and rebuild MCFW with it I have a very strange error:

After execute "make sys_all" and after u-boot, kernel and syslink successfull compilation:
===============================================================================
...
error #10281-D: Section ".bss" requires a STATIC_BASE relative relocation, but
   is located at 0xc1649000, which is probably out of range of the STATIC_BASE.
   STATIC_BASE is located at 0xc1649000. Might be required to correct
   placement of ".bss" so it lies within 0x8000 of the STATIC_BASE.
error #10281-D: Section ".neardata" requires a STATIC_BASE relative relocation,
   but is located at 0xc171e084, which is probably out of range of the
   STATIC_BASE. STATIC_BASE is located at 0xc1649000. Might be required to
   correct   placement of ".neardata" so it lies within 0x8000 of the
   STATIC_BASE.
error #10281-D: Section ".rodata" requires a STATIC_BASE relative relocation,
   but is located at 0xc171e0c0, which is probably out of range of the
   STATIC_BASE. STATIC_BASE is located at 0xc1649000. Might be required to
   correct   placement of ".rodata" so it lies within 0x8000 of the
   STATIC_BASE.
error #10010: errors encountered during linking;
   "/home/marat/workdir/SmartCore/trunk/dvr_rdk/build/dvr_rdk/bin/ti814x-scp/dv
   r_rdk_c6xdsp_debug_2048M_512M.xe674" not built
....
=================================================================================

Please help me to fix this problem.
I don't clearly understood where is STATIC_BASE defined and what I need to change on Sys/BIOS level for complete compile my code.

My memory configuration file attached. Please just rename "config_2G.txt" to "config_2G.bld"

Fullscreen 4718.config_2G.txt Download

/*
 *  ======== config.bld ========
 *  Build configuration script for HDVPSS drivers
 */

/* load the required modules for the configuration */

var M3 = xdc.useModule('ti.targets.arm.elf.M3');
var C674 = xdc.useModule('ti.targets.elf.C674');

var buildReleaseConfig = true;

/* configure  the options for the M3 targets     */

/* M3 compiler directory path                    */
M3.rootDir = java.lang.System.getenv("CGTOOLS");

/* linker options */

M3.lnkOpts.suffix += " --zero_init=off ";
M3.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";

/* compiler options                                */
M3.ccOpts.suffix += "  --gcc -DTI_814X_BUILD -DPLATFORM_EVM_SI -DSYSLINK_BUILD_RTOS -DUSE_SYSLINK_NOTIFY=0 -DUTILS_ASSERT_ENABLE -DSCP_DDR_MEM_SIZE_2G";

/* set default platform and list of all interested
 * platforms for M3
 */
M3.platforms = [
                        "ti.platforms.evmTI814X:core0",
                        "ti.platforms.evmTI814X:core1",
               ];

/* Select the default platform
 *
 * Making core1 as defualt core configuration to be used
 *  Core 0 ==    Ducati.M3.VIDEO
 *  Core 1 ==    Ducati.M3.VPS
 */
M3.platform = M3.platforms[1];

/* configure  the options for the C674 targets     */

/* C674 compiler directory path                    */
C674.rootDir = java.lang.System.getenv("CGTOOLS_DSP");

/* linker options */

C674.lnkOpts.suffix += " --zero_init=off ";
C674.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";

/* compiler options                                */
C674.ccOpts.suffix += " -DTI_814X_BUILD -DPLATFORM_EVM_SI -DSYSLINK_BUILD_RTOS -DUSE_SYSLINK_NOTIFY=0";

C674.platforms = ["ti.platforms.evmTI816X:plat"];
C674.platform = C674.platforms[0];

/* list interested targets in Build.targets array  */
Build.targets = [
                    M3,
                    C674,
                ];



var KB=1024;
var MB=KB*KB;
var GB=KB*KB*KB;

var DDR3_ADDR            = 0x80000000;
var DDR3_SIZE            = 2048*MB;
var DDR3_ADDR_REG0_START = 0x80000000;
var DDR3_ADDR_REG0_END   = 0xBFFFFFFF;
var DDR3_ADDR_REG1_START = 0xC0000000;
var DDR3_ADDR_REG1_END   = 0xFFFFFFFF;



var OCMC0_ADDR                 = 0x40300000;
/*OCMC1 exisits only for TI816X*/
var OCMC1_ADDR                 = 0x40400000;
var OCMC_SIZE                  = 128*KB;

var OCMC0_VIDEO_M3_SIZE        = 16*KB;
var OCMC0_VPSS_M3_SIZE         = OCMC_SIZE - OCMC0_VIDEO_M3_SIZE;

var OCMC0_VIDEO_M3_ADDR        = OCMC0_ADDR;
var OCMC0_VPSS_M3_ADDR          = OCMC0_VIDEO_M3_ADDR + OCMC0_VIDEO_M3_SIZE;



var OCMC0_RUN_ADDR             = 0x00300000;
var OCMC0_VIDEO_M3_RUN         = OCMC0_RUN_ADDR;
var OCMC0_VPSS_M3_RUN          = OCMC0_VIDEO_M3_RUN + OCMC0_VIDEO_M3_SIZE;

var M3_L2_RAM              = 0x55024000;
var M3_L2_RAM_SIZE         = 48*KB;

var M3_L2_RAM_MAPPED          = 0x20004000;

var TOTAL_MEM_SIZE             = 2048*MB;

/* =================================== */
/* FIRST 512MB */
var SR1_SIZE                   = 384*MB;
var VIDEO_M3_CODE_SIZE         = 8*MB 
var VIDEO_M3_DATA_SIZE         = 24*MB;
var VIDEO_M3_BSS_SIZE          = 32*MB;
var DSS_M3_CODE_SIZE           = 8*MB;
var DSS_M3_DATA_SIZE           = 24*MB;
var DSS_M3_BSS_SIZE            = 32*MB
/* =================================== */

/* =================================== */
/* SECOND 512MB */
var TILER_SIZE                 = 256*MB; /* MUST be aligned on 128MB boundary */
var SR2_FRAME_BUFFER_SIZE      = 256*MB;  
/* =================================== */

/* =================================== */
/* THIRD 512MB */
var DSP_CODE_SIZE              = 16*MB;
var DSP_DATA_SIZE              = 476*MB;
var SR0_SIZE                   = 12*MB;
var VIDEO_M3_EXCEPTION_CTX_SIZE = 512*KB;
var VPSS_M3_EXCEPTION_CTX_SIZE = 512*KB;
var HDVPSS_DESC_SIZE           = 2*MB;
var HDVPSS_SHARED_SIZE         = 2*MB;
var NOTIFY_SHARED_SIZE         = 2*MB;
var REMOTE_DEBUG_SIZE          = 1*MB;
/* =================================== */

/* =================================== */
/* LAST 512 MB */
var LINUX_SIZE                 = 512*MB;
/* =================================== */


print ("                                                         "); 
print ("SmartCore Memory Map - 2GB DDR [4 x 512MB regions], 512MB for Linux:");
print ("                                                         "); 
print ("  0x80000000 ----+-------------------+");
print ("         ^       |  " + (SR1_SIZE / MB) + "MB            | (SR1) Bitstream buffer");
print ("         |       |                   | Cached on A8. Cached on M3, although access by DMAs");
print ("         |       +-------------------+ ");
print ("         |       |   " + (VIDEO_M3_CODE_SIZE / MB) + " MB            | Video M3 Code");
print ("       512MB     +-------------------+");
print ("         |       |   " + (VIDEO_M3_DATA_SIZE / MB) + " MB           | Video  M3 Data");
print ("         |       +-------------------+");
print ("         |       |   " + (DSS_M3_CODE_SIZE/ MB) + " MB            | VPSS  M3 Code");
print ("         |       +-------------------+");
print ("         v       |   " + (DSS_M3_DATA_SIZE/ MB) + " MB           | VPSS  M3 Data");
print ("  0xA0000000 ----+-------------------+");
print ("         ^       |                   |");
print ("         |       |   " + (TILER_SIZE / MB) + " MB          | Tiled 8-bit + 16-bit region");
print ("       512MB     |                   |");
print ("         |       +-------------------+");
print ("         v       |  "  + (SR2_FRAME_BUFFER_SIZE / MB) + " MB           | (SR2) Frame Buffer Region - <VPSS - Video M3 Frame Buf>");
print ("  0xC0000000 ----+-------------------+  ");
print ("         ^       |   " + ( DSP_CODE_SIZE / KB) + " KB         | DSP Code");
print ("         |       +-------------------+");
print ("         |       |   " + (DSP_DATA_SIZE / MB) + " MB          | DSP Data");
print ("         |       +-------------------+");
print ("         |       |                   |");
print ("       512MB     |  " + (SR0_SIZE / MB) + " MB            | (SR0) Syslink MsgQ/IPC List MP - <Non-cached on M3>");
print ("         |       +-------------------+");
print ("         |       |  " + (VIDEO_M3_EXCEPTION_CTX_SIZE / KB) + " KB           | Video M3 exception context");
print ("         |       +-------------------+  ");
print ("         |       |  " + (VPSS_M3_EXCEPTION_CTX_SIZE / KB) + "KB            | Vpss M3 exception context");
print ("         |       +-------------------+  ");
print ("         |       |  " + (HDVPSS_DESC_SIZE / MB) + " MB             | VPSS M3 - VPDMA Descriptor");
print ("         |       +-------------------+");
print ("         |       |  " + (HDVPSS_SHARED_SIZE / MB) + " MB             | VPSS M3 - FBDev Shared Memory");
print ("         |       +-------------------+");
print ("         |       |  " + (NOTIFY_SHARED_SIZE / MB) + " MB             | Host - VPSS M3 Notify(For FBDev)");
print ("         |       +-------------------+");
print ("         v       |  " + (REMOTE_DEBUG_SIZE / MB) + " MB             | Remote Debug Print");
print ("  0xE0000000 ----+-------------------+");
print ("         ^       |                   |");
print ("         |       |  " + (LINUX_SIZE / MB) + " MB           | Linux");
print ("       512MB     |                   |");
print ("         |       |                   |"); 
print ("         v       |                   |");
print ("  0xFFFFFFFF ----+-------------------+");  
print ("                                                         "); 

var SR1_ADDR                   = DDR3_ADDR_REG0_START;
var VIDEO_M3_CODE_ADDR         = SR1_ADDR                   + SR1_SIZE;
var VIDEO_M3_DATA_ADDR         = VIDEO_M3_CODE_ADDR         + VIDEO_M3_CODE_SIZE;
var VIDEO_M3_BSS_ADDR          = VIDEO_M3_DATA_ADDR         + VIDEO_M3_DATA_SIZE;

/*
    VIDEO_M3_BSS_ADDR_RUN is the translated address for VIDEO_M3_BSS_ADDR in the 
    0x20000000 region. Its assumed VIDEO_M3_BSS_ADDR lies in 0x80000000 region
*/
var VIDEO_M3_BSS_ADDR_RUN      = VIDEO_M3_BSS_ADDR - DDR3_ADDR + 0x20000000;
 
var DSS_M3_CODE_ADDR          = VIDEO_M3_BSS_ADDR         + VIDEO_M3_BSS_SIZE;
var DSS_M3_DATA_ADDR          = DSS_M3_CODE_ADDR           + DSS_M3_CODE_SIZE;
var DSS_M3_BSS_ADDR           = DSS_M3_DATA_ADDR           + DSS_M3_DATA_SIZE;
var DSS_M3_BSS_RUN            = DSS_M3_BSS_ADDR - DDR3_ADDR + 0x20000000;

var TILER_ADDR                  = DSS_M3_BSS_ADDR + DSS_M3_BSS_SIZE;
var SR2_FRAME_BUFFER_ADDR       = TILER_ADDR                    + TILER_SIZE;

var DSP_CODE_ADDR             = DDR3_ADDR_REG1_START;
var DSP_DATA_ADDR             = DSP_CODE_ADDR              + DSP_CODE_SIZE;
if ((DSP_DATA_ADDR + DSP_DATA_SIZE) > DDR3_ADDR_REG1_END)
{
  throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                           "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_ADDR_REG1_END) + 
                           "\nActual End: " + "0x" + java.lang.Long.toHexString(DSP_DATA_ADDR + DSP_DATA_SIZE));
}

var SR0_ADDR                    = DSP_DATA_ADDR               + DSP_DATA_SIZE;
var VIDEO_M3_EXCEPTION_CTX_ADDR = SR0_ADDR                    + SR0_SIZE;
var VPSS_M3_EXCEPTION_CTX_ADDR  = VIDEO_M3_EXCEPTION_CTX_ADDR + VIDEO_M3_EXCEPTION_CTX_SIZE;
var HDVPSS_DESC_ADDR            = VPSS_M3_EXCEPTION_CTX_ADDR  + VPSS_M3_EXCEPTION_CTX_SIZE;
var HDVPSS_SHARED_ADDR          = HDVPSS_DESC_ADDR            + HDVPSS_DESC_SIZE;
var NOTIFY_SHARED_ADDR          = HDVPSS_SHARED_ADDR          + HDVPSS_SHARED_SIZE;
var REMOTE_DEBUG_ADDR           = NOTIFY_SHARED_ADDR          + NOTIFY_SHARED_SIZE;

if ((VPSS_M3_EXCEPTION_CTX_ADDR + VPSS_M3_EXCEPTION_CTX_SIZE) > HDVPSS_SHARED_ADDR)
{
  print(" ### DSP_CODE_ADDR                    = " + java.lang.Long.toHexString(DSP_CODE_ADDR));
  print(" ### DSP_DATA_ADDR                    = " + java.lang.Long.toHexString(DSP_DATA_ADDR));
  print(" ### SR0_ADDR                         = " + java.lang.Long.toHexString(SR0_ADDR));
  print(" ### VIDEO_M3_EXCEPTION_CTX_ADDR      = " + java.lang.Long.toHexString(VIDEO_M3_EXCEPTION_CTX_ADDR));
  print(" ### VPSS_M3_EXCEPTION_CTX_ADDR       = " + java.lang.Long.toHexString(VP0SS_M3_EXCEPTION_CTX_ADDR));
  print(" ### HDVPSS_DESC_ADDR                 = " + java.lang.Long.toHexString(HDVPSS_DESC_ADDR));
  print(" ### HDVPSS_SHARED_ADDR               = " + java.lang.Long.toHexString(HDVPSS_SHARED_ADDR));
   
  throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                           "\nRegion End: " + "0x" + java.lang.Long.toHexString(SR0_ADDR + SR0_SIZE) + 
                           "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR ));
}

var LINUX_ADDR                 = REMOTE_DEBUG_ADDR + REMOTE_DEBUG_SIZE;


/*
if ((REMOTE_DEBUG_ADDR + REMOTE_DEBUG_SIZE) > (DDR3_ADDR_REG1_END - LINUX_SIZE + 1))
{
  throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                           "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_ADDR_REG1_END) + 
                           "\nActual End: " + "0x" + java.lang.Long.toHexString(REMOTE_DEBUG_ADDR + REMOTE_DEBUG_SIZE ));
}
*/

var TOTAL_DDR_USED_SIZE_IN_MB  = ((((REMOTE_DEBUG_ADDR + REMOTE_DEBUG_SIZE) - DDR3_ADDR_REG1_START)) + ((DSP_DATA_ADDR + DSP_DATA_SIZE) - DDR3_ADDR_REG1_START))/MB;

print(" ### ");
print(" ### REGIONS MAP: ###");
print(" ======== First 512 MB: ================================= ");
print(" ### SR1:                         0x" + java.lang.Long.toHexString(SR1_ADDR) + " - 0x" + java.lang.Long.toHexString(SR1_ADDR+SR1_SIZE));
print(" ### VIDEO_M3_CODE_ADDR:          0x" + java.lang.Long.toHexString(VIDEO_M3_CODE_ADDR) + " - 0x" + java.lang.Long.toHexString(VIDEO_M3_CODE_ADDR+VIDEO_M3_CODE_SIZE));
print(" ### VIDEO_M3_DATA_ADDR:          0x" + java.lang.Long.toHexString(VIDEO_M3_DATA_ADDR) + " - 0x" + java.lang.Long.toHexString(VIDEO_M3_DATA_ADDR+VIDEO_M3_DATA_SIZE));
print(" ### DSS_M3_CODE_ADDR:            0x" + java.lang.Long.toHexString(DSS_M3_CODE_ADDR) + " - 0x" + java.lang.Long.toHexString(DSS_M3_CODE_ADDR+DSS_M3_CODE_SIZE));
print(" ### DSS_M3_DATA_ADDR:            0x" + java.lang.Long.toHexString(DSS_M3_DATA_ADDR) + " - 0x" + java.lang.Long.toHexString(DSS_M3_DATA_ADDR+DSS_M3_DATA_SIZE));
print(" ======== Second 512 MB: ================================= ");
print(" ### TILER_ADDR:                  0x" + java.lang.Long.toHexString(TILER_ADDR) + " - 0x" + java.lang.Long.toHexString(TILER_ADDR+TILER_SIZE));
print(" ### SR2_FRAME_BUFFER_ADDR:       0x" + java.lang.Long.toHexString(SR2_FRAME_BUFFER_ADDR) + " - 0x" + java.lang.Long.toHexString(SR2_FRAME_BUFFER_ADDR+SR2_FRAME_BUFFER_SIZE));
print(" ========= Third 512 MB: ================================== ");
print(" ### DSP_CODE_ADDR:               0x" + java.lang.Long.toHexString(DSP_CODE_ADDR) + " - 0x" + java.lang.Long.toHexString(DSP_CODE_ADDR+DSP_CODE_SIZE));
print(" ### DSP_DATA_ADDR:               0x" + java.lang.Long.toHexString(DSP_DATA_ADDR) + " - 0x" + java.lang.Long.toHexString(DSP_DATA_ADDR+DSP_DATA_SIZE));
print(" ### SR0_ADDR:                    0x" + java.lang.Long.toHexString(SR0_ADDR) + " - 0x" + java.lang.Long.toHexString(SR0_ADDR+SR0_SIZE));
print(" ### VIDEO_M3_EXCEPTION_CTX_ADDR: 0x" + java.lang.Long.toHexString(VIDEO_M3_EXCEPTION_CTX_ADDR) + " - 0x" + java.lang.Long.toHexString(VIDEO_M3_EXCEPTION_CTX_ADDR+VIDEO_M3_EXCEPTION_CTX_SIZE));
print(" ### VPSS_M3_EXCEPTION_CTX_ADDR:  0x" + java.lang.Long.toHexString(VPSS_M3_EXCEPTION_CTX_ADDR) + " - 0x" + java.lang.Long.toHexString(VPSS_M3_EXCEPTION_CTX_ADDR+VPSS_M3_EXCEPTION_CTX_SIZE));
print(" ### HDVPSS_DESC_ADDR:            0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR) + " - 0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR+HDVPSS_DESC_SIZE));
print(" ### HDVPSS_SHARED_ADDR:          0x" + java.lang.Long.toHexString(HDVPSS_SHARED_ADDR) + " - 0x" + java.lang.Long.toHexString(HDVPSS_SHARED_ADDR+HDVPSS_SHARED_SIZE));
print(" ### NOTIFY_SHARED_ADDR:          0x" + java.lang.Long.toHexString(NOTIFY_SHARED_ADDR) + " - 0x" + java.lang.Long.toHexString(NOTIFY_SHARED_ADDR+NOTIFY_SHARED_SIZE));
print(" ### REMOTE_DEBUG_ADDR:           0x" + java.lang.Long.toHexString(REMOTE_DEBUG_ADDR) + " - 0x" + java.lang.Long.toHexString(REMOTE_DEBUG_ADDR+REMOTE_DEBUG_SIZE));
print(" ======== Last 512 MB: ================================== ");
print(" ### LINUX:                       0x" + java.lang.Long.toHexString(LINUX_ADDR) + " - 0x" + java.lang.Long.toHexString(LINUX_ADDR+LINUX_SIZE-1));
print(" ========================================================= ");
print(" ### ");
print(" ========================================================= ");
print(" ### Total DDR usage in MB = " + TOTAL_DDR_USED_SIZE_IN_MB + " MB ###");
print(" ========================================================= ");
print(" ### ");

Build.platformTable["ti.platforms.evmTI814X:core1"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len:  DDR3_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len:  OCMC_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC_SIZE
        }],
        ["M3_L2_RAM", {
            comment: "M3_L2_RAM",
            name: "M3_L2_RAM",
            base: M3_L2_RAM,
            len:  M3_L2_RAM_SIZE
        }],
        ["OCMC0_RAM_MAPPED", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM_MAPPED",
            base: OCMC0_RUN_ADDR,
            len:  OCMC_SIZE
        }],         
        ["CACHE_WB_DDR_LOGICAL_ADDRESS", {
            comment: "CACHE_WB_DDR_LOGICAL_ADDRESS",
            name: "CACHE_WB_DDR_LOGICAL_ADDRESS",
            base: 0x20000000,
            len:  0x20000000,
        }],       
    ],
    customMemoryMap:
    [
        ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["VIDEO_M3_DATA_MEM", {
            comment : "VIDEO_M3_DATA_MEM",
            name    : "VIDEO_M3_DATA_MEM",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["VIDEO_M3_BSS_ADDR", {
            comment : "VIDEO_M3_BSS_ADDR",
            name    : "VIDEO_M3_BSS_ADDR",
            base    : VIDEO_M3_BSS_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["VIDEO_M3_BSS_ADDR_RUN", {
            comment : "VIDEO_M3_BSS_ADDR_RUN",
            name    : "VIDEO_M3_BSS_ADDR_RUN",
            base    : VIDEO_M3_BSS_ADDR_RUN,
            len     : VIDEO_M3_BSS_SIZE
        }],
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DDR3_M3", {
            comment : "DDR3_M3",
            name    : "DDR3_M3",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["DSS_M3_BSS_ADDR", {
            comment : "DSS_M3_BSS_ADDR",
            name    : "DSS_M3_BSS_ADDR",
            base    : DSS_M3_BSS_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],        
        ["DSS_M3_BSS_ADDR_RUN", {
            comment : "DSS_M3_BSS_ADDR_RUN",
            name    : "DSS_M3_BSS_ADDR_RUN",
            base    : DSS_M3_BSS_RUN,
            len     : DSS_M3_BSS_SIZE
        }],        
         ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["VIDEO_M3_EXCEPTION_CTX", {
            comment : "VIDEO_M3_EXCEPTION_CTX",
            name    : "VIDEO_M3_EXCEPTION_CTX",
            base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
            len     : VIDEO_M3_EXCEPTION_CTX_SIZE
        }],
        ["VPSS_M3_EXCEPTION_CTX", {
            comment : "VPSS_M3_EXCEPTION_CTX",
            name    : "VPSS_M3_EXCEPTION_CTX",
            base    : VPSS_M3_EXCEPTION_CTX_ADDR,
            len     : VPSS_M3_EXCEPTION_CTX_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["L2_ROM", {
            comment: "L2_ROM",
            name: "L2_ROM",
            base: 0x00000000,
            len:  0x00004000
        }],
        ["OCMC0_VIDEO_M3_RAM", {
            comment: "OCMC0_VIDEO_M3_RAM",
            name: "OCMC0_VIDEO_M3_RAM",
            base: OCMC0_VIDEO_M3_ADDR,
            len:  OCMC0_VIDEO_M3_SIZE
        }],
        ["OCMC0_VPSS_M3_RAM", {
            comment: "OCMC0_VPSS_M3_RAM",
            name: "OCMC0_VPSS_M3_RAM",
            base: OCMC0_VPSS_M3_ADDR,
            len:  OCMC0_VPSS_M3_SIZE
        }],        
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC_SIZE
        }],
        ["M3_L2_RAM", {
            comment: "M3_L2_RAM",
            name: "M3_L2_RAM",
            base: M3_L2_RAM,
            len:  M3_L2_RAM_SIZE
        }],
        ["M3_L2_RAM_MAPPED", {
            comment: "M3_L2_RAM",
            name: "M3_L2_RAM_MAPPED",
            base: M3_L2_RAM_MAPPED,
            len:  M3_L2_RAM_SIZE
        }],
        ["OCMC0_VIDEO_M3_RAM_MAPPED", {
            comment: "OCMC0_VIDEO_M3_RAM_MAPPED",
            name: "OCMC0_VIDEO_M3_RAM_MAPPED",
            base: OCMC0_VIDEO_M3_RUN,
            len:  OCMC0_VIDEO_M3_SIZE
        }],
        ["OCMC0_VPSS_M3_RAM_MAPPED", {
            comment: "OCMC0_VPSS_M3_RAM_MAPPED",
            name: "OCMC0_VPSS_M3_RAM_MAPPED",
            base: OCMC0_VPSS_M3_RUN,
            len:  OCMC0_VPSS_M3_SIZE
        }], 
    ]
};

Build.platformTable["ti.platforms.evmTI814X:core0"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len:  DDR3_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len:  OCMC_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC_SIZE
        }],
        ["M3_L2_RAM", {
            comment: "M3_L2_RAM",
            name: "M3_L2_RAM",
            base: M3_L2_RAM,
            len:  M3_L2_RAM_SIZE
        }],   
       ["OCMC0_RAM_MAPPED", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM_MAPPED",
            base: OCMC0_RUN_ADDR,
            len:  OCMC_SIZE
        }],
        ["CACHE_WB_DDR_LOGICAL_ADDRESS", {
            comment: "CACHE_WB_DDR_LOGICAL_ADDRESS",
            name: "CACHE_WB_DDR_LOGICAL_ADDRESS",
            base: 0x20000000,
            len:  0x20000000,
        }],          
        
    ],
    customMemoryMap:
    [
        ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["DDR3_M3", {
            comment : "DDR3_M3",
            name    : "DDR3_M3",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["VIDEO_M3_BSS_ADDR", {
            comment : "VIDEO_M3_BSS_ADDR",
            name    : "VIDEO_M3_BSS_ADDR",
            base    : VIDEO_M3_BSS_ADDR,
            len     : VIDEO_M3_BSS_SIZE
        }],          
        ["VIDEO_M3_BSS_ADDR_RUN", {
            comment : "VIDEO_M3_BSS_ADDR_RUN",
            name    : "VIDEO_M3_BSS_ADDR_RUN",
            base    : VIDEO_M3_BSS_ADDR_RUN,
            len     : VIDEO_M3_BSS_SIZE
        }],          
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DSS_M3_DATA_MEM", {
            comment : "DSS_M3_DATA_MEM",
            name    : "DSS_M3_DATA_MEM",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["DSS_M3_BSS_ADDR", {
            comment : "DSS_M3_BSS_ADDR",
            name    : "DSS_M3_BSS_ADDR",
            base    : DSS_M3_BSS_ADDR,
            len     : DSS_M3_BSS_SIZE
        }],        
        ["DSS_M3_BSS_ADDR_RUN", {
            comment : "DSS_M3_BSS_ADDR_RUN",
            name    : "DSS_M3_BSS_ADDR_RUN",
            base    : DSS_M3_BSS_RUN,
            len     : DSS_M3_BSS_SIZE
        }],        

        ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["VIDEO_M3_EXCEPTION_CTX", {
            comment : "VIDEO_M3_EXCEPTION_CTX",
            name    : "VIDEO_M3_EXCEPTION_CTX",
            base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
            len     : VIDEO_M3_EXCEPTION_CTX_SIZE
        }],
        ["VPSS_M3_EXCEPTION_CTX", {
            comment : "VPSS_M3_EXCEPTION_CTX",
            name    : "VPSS_M3_EXCEPTION_CTX",
            base    : VPSS_M3_EXCEPTION_CTX_ADDR,
            len     : VPSS_M3_EXCEPTION_CTX_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["L2_ROM", {
            comment: "L2_ROM",
            name: "L2_ROM",
            base: 0x00000000,
            len:  0x00004000
        }],
        ["OCMC0_VIDEO_M3_RAM", {
            comment: "OCMC0_VIDEO_M3_RAM",
            name: "OCMC0_VIDEO_M3_RAM",
            base: OCMC0_VIDEO_M3_ADDR,
            len:  OCMC0_VIDEO_M3_SIZE
        }],
        ["OCMC0_VPSS_M3_RAM", {
            comment: "OCMC0_VPSS_M3_RAM",
            name: "OCMC0_VPSS_M3_RAM",
            base: OCMC0_VPSS_M3_ADDR,
            len:  OCMC0_VPSS_M3_SIZE
        }], 
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC_SIZE
        }],
        ["M3_L2_RAM", {
            comment: "M3_L2_RAM",
            name: "M3_L2_RAM",
            base: M3_L2_RAM,
            len:  M3_L2_RAM_SIZE
        }],
        ["M3_L2_RAM_MAPPED", {
            comment: "M3_L2_RAM",
            name: "M3_L2_RAM_MAPPED",
            base: M3_L2_RAM_MAPPED,
            len:  M3_L2_RAM_SIZE
        }], 
        ["OCMC0_VIDEO_M3_RAM_MAPPED", {
            comment: "OCMC0_VIDEO_M3_RAM_MAPPED",
            name: "OCMC0_VIDEO_M3_RAM_MAPPED",
            base: OCMC0_VIDEO_M3_RUN,
            len:  OCMC0_VIDEO_M3_SIZE
        }],
        ["OCMC0_VPSS_M3_RAM_MAPPED", {
            comment: "OCMC0_VPSS_M3_RAM_MAPPED",
            name: "OCMC0_VPSS_M3_RAM_MAPPED",
            base: OCMC0_VPSS_M3_RUN,
            len:  OCMC0_VPSS_M3_SIZE
        }],       
    ]
};

Build.platformTable["ti.platforms.evmTI814X:plat"] =
{
    externalMemoryMap:
    [
        ["DDR3_RAM", {
            comment: "DDR3_RAM",
            name: "DDR3_RAM",
            base: DDR3_ADDR,
            len:  DDR3_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len:  OCMC_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC_SIZE
        }],
    ],
    customMemoryMap:
    [
        ["LINUX_MEM", {
            comment : "LINUX_MEM",
            name    : "LINUX_MEM",
            base    : LINUX_ADDR,
            len     : LINUX_SIZE
        }],
        ["SR1", {
            comment : "SR1",
            name    : "SR1",
            base    : SR1_ADDR,
            len     : SR1_SIZE
        }],
        ["VIDEO_M3_CODE_MEM", {
            comment : "VIDEO_M3_CODE_MEM",
            name    : "VIDEO_M3_CODE_MEM",
            base    : VIDEO_M3_CODE_ADDR,
            len     : VIDEO_M3_CODE_SIZE
        }],
        ["VIDEO_M3_DATA_MEM", {
            comment : "VIDEO_M3_DATA_MEM",
            name    : "VIDEO_M3_DATA_MEM",
            base    : VIDEO_M3_DATA_ADDR,
            len     : VIDEO_M3_DATA_SIZE
        }],
        ["DSS_M3_CODE_MEM", {
            comment : "DSS_M3_CODE_MEM",
            name    : "DSS_M3_CODE_MEM",
            base    : DSS_M3_CODE_ADDR,
            len     : DSS_M3_CODE_SIZE
        }],
        ["DSS_M3_DATA_MEM", {
            comment : "DSS_M3_DATA_MEM",
            name    : "DSS_M3_DATA_MEM",
            base    : DSS_M3_DATA_ADDR,
            len     : DSS_M3_DATA_SIZE
        }],
        ["TILER_MEM", {
            comment : "TILER_MEM",
            name    : "TILER_MEM",
            base    : TILER_ADDR,
            len     : TILER_SIZE
        }],
        ["SR2_FRAME_BUFFER_MEM", {
            comment : "SR2_FRAME_BUFFER_MEM",
            name    : "SR2_FRAME_BUFFER_MEM",
            base    : SR2_FRAME_BUFFER_ADDR,
            len     : SR2_FRAME_BUFFER_SIZE
        }],
        ["DSP_CODE_MEM", {
            comment : "DSP_CODE_MEM",
            name    : "DSP_CODE_MEM",
            base    : DSP_CODE_ADDR,
            len     : DSP_CODE_SIZE
        }],
        ["DSP_DATA_MEM", {
            comment : "DDR3_DSP",
            name    : "DDR3_DSP",
            base    : DSP_DATA_ADDR,
            len     : DSP_DATA_SIZE
        }],
        ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }],
        ["VIDEO_M3_EXCEPTION_CTX", {
            comment : "VIDEO_M3_EXCEPTION_CTX",
            name    : "VIDEO_M3_EXCEPTION_CTX",
            base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
            len     : VIDEO_M3_EXCEPTION_CTX_SIZE
        }],
        ["VPSS_M3_EXCEPTION_CTX", {
            comment : "VPSS_M3_EXCEPTION_CTX",
            name    : "VPSS_M3_EXCEPTION_CTX",
            base    : VPSS_M3_EXCEPTION_CTX_ADDR,
            len     : VPSS_M3_EXCEPTION_CTX_SIZE
        }],
        ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }],
        ["HDVPSS_SHARED_MEM", {
            comment : "HDVPSS_SHARED_MEM",
            name    : "HDVPSS_SHARED_MEM",
            base    : HDVPSS_SHARED_ADDR,
            len     : HDVPSS_SHARED_SIZE
        }],
        ["HOST_VPSS_NOTIFYMEM", {
            comment : "HOST_VPSS_NOTIFYMEM",
            name    : "HOST_VPSS_NOTIFYMEM",
            base    : NOTIFY_SHARED_ADDR,
            len     : NOTIFY_SHARED_SIZE
        }],
        ["REMOTE_DEBUG_MEM", {
            comment : "REMOTE_DEBUG_MEM",
            name    : "REMOTE_DEBUG_MEM",
            base    : REMOTE_DEBUG_ADDR,
            len     : REMOTE_DEBUG_SIZE
        }],
        ["OCMC0_RAM", {
            comment: "OCMC0_RAM",
            name: "OCMC0_RAM",
            base: OCMC0_ADDR,
            len:  OCMC_SIZE
        }],
        ["OCMC1_RAM", {
            comment: "OCMC1_RAM",
            name: "OCMC1_RAM",
            base: OCMC1_ADDR,
            len:  OCMC_SIZE
        }],
        ["DSP_L2_RAM", {
            comment: "DSP_L2_RAM",
            name: "DSP_L2_RAM",
            base: 0x10800000,
            len:  0x00020000
        }],
    ],
    l1PMode: "32k",
    l1DMode: "32k",
    l2Mode:  "128k"
};

var addrFileGenerated = false;
if (addrFileGenerated == false)
{
    xdc.loadCapsule("genaddrinfo.xs").GenAddrFile();
    addrFileGenerated = true;
}

Please see to attached created map file

over 11 years ago

0 Marat Shchuchinsky over 11 years ago

Expert 2595 points

This is memory partitionig created by me for 2GB memory size (LInux removed from first to last 512MB region, and DSP started from REG3: 0xC0000000)

======== First 512 MB: =================================
### SR1:                         0x80000000 - 0x98000000
### VIDEO_M3_CODE_ADDR:          0x98000000 - 0x98800000
### VIDEO_M3_DATA_ADDR:          0x98800000 - 0x9a000000
### DSS_M3_CODE_ADDR:            0x9c000000 - 0x9c800000
### DSS_M3_DATA_ADDR:            0x9c800000 - 0x9e000000
======== Second 512 MB: =================================
### TILER_ADDR:                  0xa0000000 - 0xb0000000
### SR2_FRAME_BUFFER_ADDR:       0xb0000000 - 0xc0000000
========= Third 512 MB: ==================================
### DSP_CODE_ADDR:               0xc0000000 - 0xc1000000
### DSP_DATA_ADDR:               0xc1000000 - 0xdec00000
### SR0_ADDR:                    0xdec00000 - 0xdf800000
### VIDEO_M3_EXCEPTION_CTX_ADDR: 0xdf800000 - 0xdf880000
### VPSS_M3_EXCEPTION_CTX_ADDR: 0xdf880000 - 0xdf900000
### HDVPSS_DESC_ADDR:            0xdf900000 - 0xdfb00000
### HDVPSS_SHARED_ADDR:          0xdfb00000 - 0xdfd00000
### NOTIFY_SHARED_ADDR:          0xdfd00000 - 0xdff00000
### REMOTE_DEBUG_ADDR:           0xdff00000 - 0xe0000000
======== Last 512 MB: ==================================
### LINUX:                       0xe0000000 - 0xffffffff
=========================================================

0 Badri Narayanan over 11 years ago in reply to Marat Shchuchinsky

TI__Guru 59700 points

The 2G memory map you have listed will not work. There are issues apart from the linking error you are facing. For 2G memory map refer /dvr_rdk/mcfw/src_bios6/cfg/ti816x/config_2G.bld. This memory map is tested on 816x .

You need to enable build define TI816X_2G_DDR which is currently only enabled for 816x 2G build in file

/dvr_rdk/component.mk

ifeq ($(DDR_MEM),DDR_MEM_2048M)
DVR_RDK_CFLAGS += -DTI816X_2G_DDR
endif

Also ensure your DMM_LISA setting is correct for 2G memory map. On 814x,in some uboot configuration the DMM_LISA settings map same physical memory on 0x8xxx_xxxx to 0xAxxx_xxxx and 0xAxxx_xxxx to 0xCxxx_xxxx

0 Marat Shchuchinsky over 11 years ago in reply to Badri Narayanan

Expert 2595 points

Hello Badri,

thanX alot for your reply. Please let me know, exist any way to run DM8148 with 2GB of physical memory (or as minimal use only 3/4 of DDR's and config for 1,5GB)? And may I ask you explain me "in deep" why my 2GB configuration file doesn't works? If 2GB tested and works on DM8168, why is porblem create 2GB configuration for DM8148. Am I understood correctly that DM814x and DM816x - both have same memory controller?

0 Badri Narayanan over 11 years ago in reply to Marat Shchuchinsky

TI__Guru 59700 points

Marat Shchuchinsky said:
Please let me know, exist any way to run DM8148 with 2GB of physical memory (or as minimal use only 3/4 of DDR's and config for 1,5GB)?

As I mentioned use the 2G memory map configuration of 816x with the changes I mentioned if you want to use 2G physical memory.

Marat Shchuchinsky said:
If 2GB tested and works on DM8168, why is porblem create 2GB configuration for DM8148. Am I understood correctly that DM814x and DM816x - both have same memory controller?

I don't understand your question. WHat issue are you facing using the ti816x 2G memory map on 814x ?

Processors

Processors forum

DM8148 with 2GB DDR3 on board. MCFW compilation failed