AM3352 and DDR3 Issue

John, if it is the exact same layout between the 2 boards, and the same memory and speed, the results of the software leveling should be similar.  Are these values drastically different?  What topology between AM3352 and the memory do you have on these boards? T-configuration, point to point? 

Also, your design that doesn't work is using a slower rated AM3352 (max ARM freq is 600MHz).  Did SPL/u-boot change to comprehend this new maximum?

Another debug method may be to break in with JTAG after ddr_config executes, run the GEL to re-configure the DDR, and see how far it gets.

Regards,

James

James, 

When we compared the values they are almost identical. It is point to point routing with the single memory chip that is on board. 

For the PLL/Clock settings I configured it as follows:

void am33xx_spl_board_init(void)

{

dll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);

do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);

do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);

}

I will try to do the JTAG test with the GEL script still set and see what happens. 

Thanks for your help, 

John

James,

I tried what you suggested, and running the JTAG with the GEL script to initialize the registers again makes it work just fine. 

So I did a little bit of digging into that and found that the GEL file had the DDR PLL value set to 303 MHz!

So oddly enough, even though all of my calculations are based on 400 MHz that file seems to be ok with 303 MHz. 

Next I changed my DDR PLL in U-Boot to 303 MHz, and now I can get it to boot up to a point when the kernel hangs, or panics. 

Finally I tried editing the GEL file to increase the MPU speed to 600 MHz and the DDR PLL to 400 MHz and re-running the software leveling tools. This produces all 0's which means something is configured wrong. I am fairly certain I have the correct register values though. 

Any thoughts?

Thanks, 

John

John, can you send me the values of SDRAM_TIM_1 thru 3 and the SDRAM _CONFIG registers?  I'll take a look...

Regards,

James

James, 

Here are the values being used.

Tim_1: 0x0AAAD4DB

Tim_2: 0x266B7FDA

Tim_3: 0x501F867F

Config: 0x61C05332

REF_CTRL: 0xC30

ZQ_CONFIG: 0x50074BE4

PHY_INVERT_CLOCK: 1

PHY_CTRL_SLAVE_RATIO: 0x100

I also tried to use the +1 non optimal values with the GEL script set to 400 MHZ and it still doesn't work. I am guessing I have a config value wrong in here somewhere. 

Thanks for all the help, 

John

OK these look good.  Forgot to ask you for one more DDR_PHY_CTRL_1.

Regards,

James

The read_latency bits of DDR_PHY_CTRL_1 register should be 0x7 when running at 400MHz.  This may be your issue and the reason why you things work better at 303MHz.

Regards,

James

James, 

We are setting ddr_phy_ctrl_1 = 0x100007;

So in theory that should be setting the latency to 7.

John

OK, thanks John.  So far it looks like everything is configured correctly.  I'd like to go back to the GEL files which you said didn't work at 400MHz

-On the original working board, can you configure the GEL file to run at MPU = 600MHz and DDR = 400MHz.  Run the software leveling and see if you get valid results.  If you do, plug those back into the GEL, reinitialize your board, and run the GEL scripts with the DDR tests.  Once you have a working GEL on the original board, use that GEL on the new boards and see if the DDR tests pass. 

I'm just trying to get to a point where the GELs work solid on both boards before trying to move back to linux. 

-what voltage level are you using for DDR on both boards?  Are both at DDR3L (1.35V)?  Check the level of VREF to ensure this is 1/2 that value and stable.

Regards,

James