Hi,
We are using a planned stack up for our Board containing DM365 SoC, MT47H64M16 DDR2 RAM and other components. Couldn't find any details mentioning Target impedance of DDR2 Differential Signals such as CK, CK#, DQS0, DQSN0, DQS1, DQSN1.
1) Please let us know if there are any requirements to follow any specific differential impedance for routing these signals.
Datasheet mentions "Center to center DQS-DQSN spacing" to be a maximum of 2W. For our planned stackup this doesn't yield a 100 ohm differential impedance. This however doesn't mention CK and CK# signals.
2) Based on our planned stackup maintaining a maximum 2W spacing will result 90ohm differential impedance for DQS-DQSN signals, other configurations results in a lower differential impedance (to the tune of 50 to 80 ohms). Is this acceptable?
3) What is the differential impedance to be followed for CK and CK#
Thanks,
Jithin