yet another question about undershoot limits on OMAP or C674x

Hi Tom,

What is the actual trace length on your board?  Are you using on- board termination? Which I/O pad are you looking at? GPIO or SDRAM bus …etc.

The causes of over shoot and under shoot are becasue of charging and discharging of parasitic capacitors may be present in long PCB trace or load capacitance and If the source impedance of a driver mismatch trace impedance, overshoot and undershoot will exist in a receiver end, it’s majorly depends upon VDD that causes the voltage to increase/decrease due to charging/discharging of the capacitor effects.

May be you can reduce the overshoot/undershoot by reducing the duty cycle or I/O toggling frequency, but there is no guaranteed to eliminate this problem completely, unless you have a proper termination. It’s all about frequency of change in logic state; we provided the bench mark for up to 20% of Signal Period at DVDD + 20%.

Yes it’s a diode (Limit clamp current that flows through the I/O's internal diode protection cells); many LVCMOS receiver includes built-in protection diodes in the I/O pad to prevent it from overshoot/Undershoot damage. But if it over-stresses the protection diodes, can cause aluminum migration in the diode contacts and eventual failure of the diodes. Nobody seems to know (or will say) under what general conditions this will happen. The maximum voltage (and maximum current) ratings for inputs remain peculiar to each vendor.

Regards

Antony

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thanks, Anthony,

Actually, we understand the cause as a transmission line effect, but it is not convenient to correct it (we use LVC buffers with built in source terminator resistors, but their valuse are a bit too low to prevent the 'shoort).

What I am hoping someone can provide is more quantitative information (e.g. why the 20%, why the Vcc reference, whether we can get relief with reduced duty cycle) about how TI's devices will tolerate it. I understand that the OMAP-L138 and TMS320C674x are electrically similar in this respect).

Hi Tom,

This value may come from the I/O cells or I/O buffer characterization and used as qualification criteria, against which the long term reliability of a device is evaluated, it varies from vendor to vendor some vendor may specified only for 10% of the signal period, normally we suggest the customer to be with the limit as specified in the datasheet for the level of robustness be guaranteed by design.

The % of duty cycle and % of overshoot/undershoot voltage to the continuous exposure may vary between vendor but all take VCC or VDD either 3.3V or 1.8V depends upon the I/O, because the overshoot /undershoot is going above or below the VCC or VDD.

You can try different value outside the specification, but that is not intended to be used as a production test and more over we will not assure it.

Beyond those voltage levels the clamping diodes start conducting and that generates heat as the input voltage & hence current increases. More heat over substantial time could degrade the chip faster

Going beyond the maximum ratings requires that you add external components to protect the device against the excessive voltage.

Regards

Antony

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