This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.


I'm reading the UPP User's Guide, section 3.5, Table 15, WAITA and WAITB descriptions. From the description of the WAITA and WAITB bit fields, I understand that the WAIT signal is only supported on Transmit mode (OMAP transmitting data) and that on receive mode the wait signal is always driven low no matter whether you drive this signal with a high or low.  Is my understanding correct?  If my understanding is not correct, then how do I configure the WAIT signal for receive mode, if I want to halt the UPP from receiving data for a a period of time?  Or must I do this via another mechanism (i.e. timers)?      

  • Joe,

    The WAIT signal allows the receiving device to request a pause in the current transmission.  However, the uPP peripheral doesn't allow the CPU to arbitrarily assert WAIT when you are operating in receive mode.  The only time that WAIT is asserted is when the peripheral is halted by emulation.  Unfortunately, this means you'll need to work out some other mechanism if you want to only receive data part of the time.  For example, you may want to receive a buffer, then perform some complicated processing on it without worrying about the next incoming buffer.  However, in this case you may also be able to queue up a second transfer and receive the next buffer while you process the current buffer.  The uPP's internal DMA could be a big help here.

    The WAITA and WAITB bits in UPICR (i.e. Table 15) allow uPP to ignore WAIT when it is operating in transmit mode.  These bits have no effect when uPP operates in receive mode.

    Hope this helps.