Disabling cache for DDR in C6678

Hi all,

I have built a multicore program for the C6678 (TMDSEVM6678L rev. 3B) and I would like to have a buffer in a non-cached memory section. So, I have put the buffer in DDR and I have disabled the cache for that DDR section. However, I still need to use CACHE_invL1d / CACHE_invL2  before reading the data in that buffer. Otherwise, I get the old values. These buffer is modified by SRIO (I have another DSP writing data to the buffer address by SRIO).

The code which I think is relevant is the following:

*** core 0: (at start-up)

CACHE_disableCaching (0x83000000 >> 24);


*** core 1: (long after the core 0 CACHE_disableCaching)

while (1)
{
    CACHE_invL1d((void *)&gCore1SRIOLocalMemoryBuffer[0], 32, CACHE_WAIT);
    CACHE_invL2 ((void*)&gCore1SRIOLocalMemoryBuffer[0], 32, CACHE_WAIT);
    if (gCore1SRIOLocalMemoryBuffer[0] == 0x77)
        break;
}

And the gCore1SRIOLocalMemoryBuffer buffer is declared this way:

#pragma DATA_SECTION(gCore1SRIOLocalMemoryBuffer, ".srio_DDR");
#pragma DATA_ALIGN (gCore1SRIOLocalMemoryBuffer, CACHE_L2_LINESIZE)
volatile uint8_t gCore1SRIOLocalMemoryBuffer[32] = {0};


*** mad_deployment.json:

{
    "name"        : "DDR3-NONCACHED",
    "vaddr"        :  "0x83000000",
    "paddr"        : ["0x803000000", "0x803000000", "0x803000000", "0x803000000", "0x803000000", "0x803000000", "0x803000000", "0x803000000"] ,
    "size"        :  "0x01000000",
    "secNamePat"      : [".srio_DDR"],
    "cores"        : [0,1,2,3,4,5,6,7],
    "permissions"    : ["UR", "UW", "SR", "SW"],  
    "cacheEnable"    : false,
    "prefetch"      : false,
    "priority"    : 0,
    "shared"    : true
},


The other DSP is sending a buffer which starts with 0x77 to the address 0x83000000 which is gCore1SRIOLocalMemoryBuffer address (I have checked it with printf). If I remove the CACHE_xxx calls, I never exit the while loop. With them, the loop exits. I think that, if the cache is disabled for the section where my buffer resides, the CACHE_xxx calls should have no effect.

Am I missing something? is there another way of disabling the cache or maybe a never-cached memory range in this DSP? Should I look for the problem in another part of my code?

By the way, I am using mcsdk_02_01_02_06 (bios_6_33_06_50, pdk_C6678_1_1_2_6).

Thanks!