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[OMAP-L138] DSP/BIOS Link's shared memory

Other Parts Discussed in Thread: OMAP-L138

Hi,

Can someone tell me what's the maximum shared memory DSP/BIOS Link can have to share between GPPApp and DSPApp?

From the programmer guide OMAP-L138, it stated it has default of 1MB, but can be increased by modifying/adding the memory table. Also, what type of memory is it and exactly is it residing on the 6748 dsp core?

 

Please advise.

Thanks,

Stephen

  • Stephen Lin said:
    Can someone tell me what's the maximum shared memory DSP/BIOS Link can have to share between GPPApp and DSPApp?

    To better understand your question, I am curious why you are asking this question, do you have particularly large buffers to share with Link?As DSPLink uses memory pools to share data between processors there can be as much memory as you allocate in your system to these pools, meaning it can be arbitrarily large up to the maximum of your memory map minus the memory needed for other software. 

    Stephen Lin said:
    Also, what type of memory is it and exactly is it residing on the 6748 dsp core?

    Typically the DSPLink pools would be placed in external memory as they may not fit internally, in the case of OMAP-L138 this would typically be DDR space.

    Note that the majority of the memory map is shared between the processors on a SoC like the OMAP-L138, the DSPLink shared memory is just a software construct to facilitate communication, so you could argue all external memory is shared, as well as most peripherals and some internal memory.

  • thanks for the detail reply.

    The reason for large shared memory is to offload huge amount of DSP computation data to the peripherals. And we need to do lots of sample rate calculation on several channels filtering, therefore needs lots of memory to handle the computational results from DSP core to the external peripherals. In our case, what's the most efficient way for those DSP data to be transferred to peripheral (external DDR in OMAP-L138)? Is it from DSP core to ARM's linux then to peripheral (vs DSP to SCR to peripheral?)??

    Second question: Even with using memory pools, it still uses the space from the external DDR memory, right? It's just doing it dynamically, so it can accomendate more than original allocated, correct? That means, in OMAP-L138, the max shared memory (for DDR2 & mDDR) is 512MB and 256MB. correct?

    Third question: Currently, the max DDR2 and mDDR in omap-l138 is listed as 512M and 128M, and are those number the max capacity allowable for this chip? Or we can put an size of DDR2 or mDDR on it as long as it's just one memory module. This is for the future expansion purpose in case we need more memory.  SDRAM is limited at 512MB, so we are looking ahead into DDR2 section.

     

    Thanks, Stephen

  • Stephen Lin said:
    In our case, what's the most efficient way for those DSP data to be transferred to peripheral (external DDR in OMAP-L138)? Is it from DSP core to ARM's linux then to peripheral (vs DSP to SCR to peripheral?)??

    The DDR2 sits off the SCR and is accessible by both the ARM and the DSP (and other DMAs).

    Stephen Lin said:
    Second question: Even with using memory pools, it still uses the space from the external DDR memory, right? It's just doing it dynamically, so it can accomendate more than original allocated, correct? That means, in OMAP-L138, the max shared memory (for DDR2 & mDDR) is 512MB and 256MB. correct?

    Yes, the memory pools are a form of dynamic memory allocation.  You avoid fragmentation like you would see in a heap.  Clearly the pools cannot be larger than the total available memory.

    Stephen Lin said:
    Third question: Currently, the max DDR2 and mDDR in omap-l138 is listed as 512M and 128M, and are those number the max capacity allowable for this chip? Or we can put an size of DDR2 or mDDR on it as long as it's just one memory module. This is for the future expansion purpose in case we need more memory.  SDRAM is limited at 512MB, so we are looking ahead into DDR2 section.

    Those are the max sizes as dictated by memory map and number of address pins.