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TCI6486 Shared L2 - Cached?

CalvinC
Intellectual 990 points

We are using the shared L2 memory to pass status information from TCI6486 Cores 1-5 back to Core0. However, updates by Core1-5 are not always visible to Core0. Is Shared L2 cached? We added CACHE_wbL1d() calls (L2 is all SRAM - no cache) but no luck. What else should we try?

Thanks-

  • 0
    TI__Genius 14680 points

    The quick answer is that SL2 is not coherent between cores and you need to manage with writeback and invalidate.  Part of this is taking care to ensure which addresses you’re using by both sender and receiver, and when you make the coherency commands.

    @Init, ensure the message buffer isn’t cached by receiver.

    Sender:
     - Write message to SL2 using Sender’s SL2 address range (either aliased or global)
     - Wb(Inv) memory using Sender’s SL2 address range (same as used for write)
     - Notify Receiver

    Receiver (after notification):
     - Read message from SL2 using receiver’s SL2 address range (either aliased or global)
     - Inv memory using receiver’s SL2 address range (same as used for read)
     - Notify Sender

    Sender knows the message is consumed.


    Best regards,
    Dave