• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 98 subscribers
  • Views 365 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DMTIMER PROBLEM

LIANG WANG102707
Expert 1415 points

I want to use the dmtimer3 to  do this thing:

when the match event ocured , set one gpio to high ,when  overflow event ocurred ,set the gpio to low.

long meter_ioctl( struct file *filp,unsigned int cmd,unsigned long arg ){ 

.......................

case start:

omap_dm_timer_stop(dmtimer_meter);
   omap_dm_timer_set_int_enable(dmtimer_meter,  OMAP_TIMER_INT_OVERFLOW|OMAP_TIMER_INT_MATCH);
   omap_dm_timer_set_load(dmtimer_meter, 1, 0xffffffff - load);
   omap_dm_timer_set_match(dmtimer_meter, 1, 0xffffffff - match); 
   omap_dm_timer_start(dmtimer_meter);

.......
  }

I init is as following:

static int __init meter_test_init(void){

 // set the clock source to system clock   

omap_dm_timer_set_source(dmtimer_meter, OMAP_TIMER_SRC_SYS_CLK);  

 // set prescalar to 1:1   omap_dm_timer_set_prescaler(dmtimer_meter, 0);    

 // figure out what IRQ our timer triggers 

 dmtimer_meter_irq = omap_dm_timer_get_irq(dmtimer_meter);   

// omap_dm_timer_set_source(dmtimer_meter, OMAP_TIMER_SRC_SYS_CLK);  printk("timer id 0x%x,irq 0x%x\n",dmtimer_meter->id,dmtimer_meter_irq);

 if (request_irq(dmtimer_meter_irq ,timer3_interrupt,IRQF_DISABLED,dev_name(dev),NULL)){   printk("request irq failed\n");  };

}

 

when i insert my module to the kernel it is fine ,but when I run the ioctl to start the timer

it complaint that :

[   34.372393] omap_timer omap_timer.3: omap2_dm_timer_set_src: 518: clk_get() sys_ck FAILED

[   78.578855] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa042038
[   78.586871] Internal error: : 1028 [#1]
[   78.590879] Modules linked in: meter(O)
[   78.594903] CPU: 0    Tainted: G           O  (3.2.0 #14)
[   78.600573] PC is at omap_dm_timer_stop+0x64/0x110
[   78.605584] LR is at omap_dm_timer_stop+0x100/0x110
[   78.610687] pc : [<c0036c8c>]    lr : [<c0036d28>]    psr: 60000013
[   78.610693] sp : ce0f5eb8  ip : 00000000  fp : ce0f5ecc
[   78.622700] r10: 00000000  r9 : ce0f4000  r8 : cf26f470
[   78.628164] r7 : 0003a980  r6 : 00017700  r5 : bf000690  r4 : cf0be140
[   78.634991] r3 : fa042014  r2 : c05e8b0c  r1 : 016e3600  r0 : 016e3600
[   78.641819] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[   78.649284] Control: 10c5387d  Table: 8f6fc019  DAC: 00000015
[   78.655294] Process meter_test (pid: 1316, stack limit = 0xce0f42f0)
[   78.661940] Stack: (0xce0f5eb8 to 0xce0f6000)
[   78.666497] 5ea0:                                                       c05e8b0c 00000001
[   78.675056] 5ec0: ce0f5eec ce0f5ed0 bf000174 c0036c34 ce914098 00000000 00004501 cf618d40
[   78.683615] 5ee0: ce0f5f74 ce0f5ef0 c00b494c bf0000d8 ce0f5fac ce0f5f00 c0008454 c001a654
[   78.692174] 5f00: ce0f5f3c 00000000 00000000 00000000 bf0003f4 cf618d48 0000002b cf26f470
[   78.700733] 5f20: 00000002 00000000 ce0f4000 00000000 ce0f5f6c ce0f5f40 c00a5b90 c00d77d8
[   78.709291] 5f40: 00000000 00000000 c005b430 00000000 00000000 00004501 cf618d40 00000003
[   78.717851] 5f60: ce0f4000 00000000 ce0f5fa4 ce0f5f78 c00b4e38 c00b48d0 00000000 00000000
[   78.726411] 5f80: 00000004 00000000 beffec68 0000849d 00000036 c00148e8 00000000 ce0f5fa8
[   78.734969] 5fa0: c0014740 c00b4dd0 00000000 beffec68 00000003 00004501 00000000 00000001
[   78.743529] 5fc0: 00000000 beffec68 0000849d 00000036 00000000 00000000 400f1000 00000000
[   78.752088] 5fe0: 4017c1b0 beffec1c 000086c9 4017c1bc 80000010 00000003 00000000 00000000
[   78.760640] Backtrace:
[   78.763218] [<c0036c28>] (omap_dm_timer_stop+0x0/0x110) from [<bf000174>] (meter_ioctl+0xa8/0x130 [meter])
[   78.773318]  r4:00000001 r3:c05e8b0c
[   78.777082] [<bf0000cc>] (meter_ioctl+0x0/0x130 [meter]) from [<c00b494c>] (do_vfs_ioctl+0x88/0x500)
[   78.786637]  r7:cf618d40 r6:00004501 r5:00000000 r4:ce914098
[   78.792579] [<c00b48c4>] (do_vfs_ioctl+0x0/0x500) from [<c00b4e38>] (sys_ioctl+0x74/0x84)
[   78.801154] [<c00b4dc4>] (sys_ioctl+0x0/0x84) from [<c0014740>] (ret_fast_syscall+0x0/0x30)
[   78.809890]  r8:c00148e8 r7:00000036 r6:0000849d r5:beffec68 r4:00000000
[   78.816923] Code: e5933000 e3130001 1afffffb e594302c (e5932024)
[   78.823339] ---[ end trace 399485379a4aa37d ]---

 

Can anyone tell me why the timer get clk failed ?

And why  omap_dm_timer_stop failed?

Thank you

 

  • 0
    TI__Mastermind 25235 points

    Hi,

    Please put some prints inside omap_dm_timer_stop() to see where is fails and why. As far as I can see the __omap_dm_timer_stop() function first checks if the timer is started, so I'm assuming the problem isn't related to stopping an already stopped timer.

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    Expert 1415 points

    Dear Miroslav:

    I have do print inside omap_dmtimer_stop(),it show that

    l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);

    this sentence lead to fail,and rate = clk_get_rate(timer->fclk); show that the rate is 24MHz

    I am also strange that  the omap_dm_timer_set_source(dmtimer_meter, OMAP_TIMER_SRC_SYS_CLK); 

    will lead to the "clk_get() sys_ck FAILED" problem.

    Do you have meet this problem before?

    Best regards

    wangl

  • 0 in reply to LIANG WANG102707
    TI__Mastermind 25235 points

    LIANG WANG102707 said:

    I have do print inside omap_dmtimer_stop(),it show that

    l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);

    this sentence lead to fail

    Looking inside the read function, it looks like if Write Posted mode is used, then the software synchronisation inside the dmtimer driver checks if there is a pending write access to the register and waits for it, but for some reason this ends up in a endless loop. I can't be 100% sure, but this is the only explanation I have from reading the source code:

        if (posted)
            while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
                cpu_relax();

    Please try to print the value of timer->pend and reg>>WPSHIFT inside this while loop. This is inside the __omap_dm_timer_read() function.

    More information about the DMTIMER Write Posted mode can be read inside the AM335x TRM, section 20.1.3.10.1.

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    Expert 1415 points

    Dear Miroslav

    It is not in post mode when I print it ,the __raw_readl（timer->func_base+(reg&0xff)）;

    fail directly.

    I wonder whether it is related to my hwmod function clock problem.

    You can see my post before:

    http://e2e.ti.com/support/arm/sitara_arm/f/791/p/340911/1197751.aspx#1197751

    [    0.093824] omap_hwmod: l3_slow: cannot be enabled (3)
    [    0.097012] omap_hwmod: l4_per: cannot be enabled (3)
    [ 0.100356] omap_hwmod: ehrpwm.0: cannot be enabled (3)
    [ 0.103541] omap_hwmod: ehrpwm.1: cannot be enabled (3)
    [ 0.106723] omap_hwmod: ehrpwm.2: cannot be enabled (3)"

    This problem still come out ,I can not find the reason.I do not know who can provide me the help to slove this problem.

     

    Best regards

    wangl

    wangl

  • 0 in reply to LIANG WANG102707
    TI__Mastermind 25235 points

    Hi,

    Please try to start the timer inside your init function. If this doesn't show any results, then the only thing I can suggest is to try to update your SDK, as I saw you are using a very old version (05.06.00.00) in your other post.

    Best regards,
    Miroslav