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AM3352 PM suspend mode

Other Parts Discussed in Thread: AM3352

Hi there,

Please let me know the VTP control register configuration in suspend mode.

I tried to use a PM suspend/resume function in our custom board. Our board have AM3352, PMIC(TPS65217C) and DDR3(2x8bit) memory.There is a difference of power consumptioin by the vtp_ctrl register configuration. if the VTP is disabled(vtp_ctrl register[6]=0) and the lock bit is set to 1 (vtp_ctrl register[4]=1) , our board can resume correctly from suspend. In this condition, the power consumption is reduced from 2W to 0.5W. However, if the VTP is disabled (vtp_ctrl register[6]=0) and the lock bit is set to 0(vtp_ctrl register[4]=0), our board can not resume correctly from suspend. In this condition, the power consumption is reduced from 2W to 0.2W. It's pretty good the power consumption of 0.5W. If possible, I want to reduce the power consumption to 0.2W.

Is there any process or configuration according to the vtp_ctrl register?

I got the suspend/resume process from CM3 firmware as follows.

http://arago-project.org/git/projects/?p=am33x-cm3.git;a=summary

our standby process is as follows.
@AM335x
1. Save EMIF power management regs
2. Save EMIF configuration
3. Put SDRAM in self-refresh
4. WFI
@Cortex-M3
5. set_ddr_reset:
   - hold DDR_RESET high via control module
6. ddr_io_suspend:
   - Weak pull down for DQ, DM
   - Weak pull down for macro CMD0/1
   - Weak pull down for macro CMD2
7. vtp_disable:
   - VTP0_CTRL_REG <- 0x00000000 (DDR3)
8. ldo_power_down:
   - MPU Power Down
9. pll_bypass
   - CORE
   - DDR
   - DISP
   - PER
   - MPU
10. MPU power domain state change
11. clkdm_sleep:
   - CLKDM_MPU


wake-up process is as follows.

@Cortex-M3
1. a8_wakeup_standby_handler
2. pll_lock
   - MPU
   - PER
   - DISP
   - DDR
   - CORE
3. ldp_power_up:
   - MPU Power Up
4. vtp_enable:
5. hwmod_enable:
   - EMIF
6. ddr_io_resume:
   - Disable the pull for CMD2/1/0
   - Disable the pull for DATA1/0
7. clear_ddr_reset:
   - make DDR_RESET low via control module
8. disable IRQs
9. pm_reset
10. enable MBX IRQ
11. hwmod_enable:
   - MPU
@AM335x

The following log shows rtcwake command result in our board.

:~# rtcwake rtcwake -d rtc1 -m standby -s 30 -v
Using UTC time.
        delta   = -1
        tzone   = 0
        tzname  = UTC
        systime = 1401790269, (UTC) Tue Jun  3 10:11:09 2014
        rtctime = 1401790270, (UTC) Tue Jun  3 10:11:10 2014
alarm 0, sys_time 1401790269, rtc_time 1401790270, seconds 30
rtcwake: wakeup from "standby" using /dev/rtc1 at Tue Jun  3 10:11:41 2014
suspend mode: standby; suspending system
:~#

Best Regards,
Kumac
  • Hi Kumac,

    This may be due to the fact that the VTP controller needs 56 Clock cycles to guarantee the VTP outputs are initially set. See section 7.3.3.3.4 of the AM335X TRM Rev. J.

  • Hi Biser,

    Thank you for your support.

    I tried to add a wait-loop more than 56 clock cycle after VTP enable, but our board could not resume correctly from suspend.

    I have a question.
    Is it required necessarily that pcin and ncin is set to 1 to enter standby?

    In the original source code, VTP_CTRL_VAL_DDR3 value is 0x0000_0000. It could not resume correctly using original value. I think it is wrong value for correct resume process. I modified VTP_CTRL_VAL_DDR3 value from 0x0000_0000 to 0x0001_0100(pcin=1,ncin=1), then our board can resume correctly. It seems the resume function is affected by pcin and ncin bit.


    The following code is vtp_disable function in the ddr.c of CM3 firmware.

    /* same offsets for SA and Aegis */
    void vtp_disable(void)
    {
        if (mem_type == MEM_TYPE_DDR2)
            __raw_writel(VTP_CTRL_VAL_DDR2, VTP0_CTRL_REG);
        else
            __raw_writel(VTP_CTRL_VAL_DDR3, VTP0_CTRL_REG);
    }

    Best Regards,
    Kumac

  • Hi Kumac,

    Factory team has asked that you send the schematics and probe the RESETn and CKE lines during suspend and resume as you change the VTP code.

  • Hi Biser,

    I probed the DDR_RESETn and DDR_CKE lines during suspend and resume. The RESETn line was always kept to high-level during suspend. There is a difference in the CKE waveform by the vtp_ctrl register value during suspend.

    When the vtp_ctrl register is set to 0x0001_0100, the CKE voltage level go to approx. 570mV during suspend. It can be satisfied low voltage level for DDR3. When the vtp_ctrl register is set to 0x0000_0000, the CKE voltage level go to approx. 730mV during suspend. It is same as VTT(VDDS/2) voltage level and it can not be satisfied low voltage level for DDR3. The attached picture shows CKE waveform.

    Waveform #1: "suspend_CKE_vtp_ctrl_set_0001_0100.jpg" shows a waveform when the vtp_ctrl register is set to 0x0001_0100 during suspend.

    Waveform #2: "suspend_CKE_vtp_ctrl_set_0000_0000.jpg" shows a waveform when the vtp_ctrl register is set to 0x0000_0000 during suspend.

    I think, resume failure is caused by the CKE voltage level. So I tried to clear the ddr_cke_ctrl bit that will be set the CKE to zero, however the CKE can not be low level during suspend. Is there any process or configuration to set the CKE to low level?

    Regarding the schematic, the CKE line have 10k ohm pull-down resistor and 33 ohm termination connected to VTT(VDDS/2). The RESETn line have 10k ohm pull-up resistor.

    Best Regards,
    Kumac

  • Hi Kumac,

    Here is the factory team comments:

    The problem is having Vtt termination on the CKE line. If he removes the termination on the CKE line, he should not have any further issues. With VTP code of 0x1, there is weak driver enabled which is able to drive and fight the termination, but with the VTP code of 0x0, the driver is tri-stated which is why he is just seeing 0.75V.

  • Hi Biser,

    I tried to remove VTT termination on the CKE line, as a result resume worked correctly in our board. In this condition, I have checked the CKE line go to low level during suspend.

    Thank you!

    Kumac