32 kHz tolerance on OMAP4430

Hello David,

#Q1: What parallel load capacitors should we use assuming parasitic board capacitance of 2pF?

C_L = ((C_X1 x C_X2) / (C_X1 + C_X2)) + C_stray

C_stray = 2pF - parasitic board capacitance

CX1 = CX2 = 12,5pF

Therefore, the C_L = 8.25pF parallel load capacitance.

Then you can calculate the trim sensitivity for your circuit PPM/pF: Trim sensitivity is a measure of the incremental fractional frequency change for an incremental change in the value of the load capacitance. Calculated by the following equation:

S = (C₁ * 1000000) / (2*C_t² )

Where C_t is the sum of C_o and C_L

Crystal parameters:

C₁  - motional capacitance of the crystal unit.

C_o - shunt capacitance

#Q2: What does the +/- 200ppm spec  means in the OMAP4430 data manual?

- Means - clock frequency stability/accuracy.  sys_32k is a slow clock that means with no stringent duty cycle and jitter requirements.

#Q3: Is there any way to obtain a much better stability than 20ppm?

Based on the DPLL requirements, you can consider a maximum input duty cycle of [40% to 60%] of the clock period and a maximum jitter at DPLL input of 1% of the clock period coming to the DPLL.

Observe the the requirements:

• Keep the crystal as close as possible to the crystal pins X1 and X2.
• Keep the trace lengths short and small to reduce capacitor loading and prevent unwanted noise
pickup.
• Place a guard ring around the crystal and tie the ring to ground to help isolate the crystal from
unwanted noise pickup.

Best reards,

Yanko

Sorry.  You have my request wrong.

We currently have a crystal with a parallel load spec of 12.5 pF - this is the crystal CL spec, not CX1 and CX2 load cap values.

We wish to know what CX1 and CX2 should be used with this crystal CL spec and an assumed parasitic capacitance of 2 pF to meet the crystal load cap spec of 12.5 pF.  Also, you did not include X1 and / or X2 input capacitance in your calculation.  This is necessary.

Please advise your recommended CX1 and CX2.

For an improved perfromance we are aware of some 32.768 TCXO products that will maintain +/- 5 ppm over temperature.  Is this advisable?

Regards

Hello David,

In your case, the values for Cx1 and Cx2 must be equal to 21pF to match C_L = 12.5pF.

However, the closest standard capacitor values is 22pF. The C_L value by 22pF Cx1 and Cx2 will be 13pF.

I suggest using C_X1 = C_X2 = 22pF capacitor.

In the designs based on OMAP4 is used TWL6030 PMIC, which is used for generating 32.768kHz clock signal.

Best regards,

Yanko

Thank you very much.

I have posted this question on the wrong forum in error.  We are using the TWL6032.  I will repost in that forum.