Interfacing OMAPL137 EMIF-B bus with SRAM (Static RAM) memory devices

Hi Srinivas,

OMAP L137 EMIFB bus support primarily SDRAM devices but i want to interface it with SRAM devices.

Can anyone please suggest what is the correct  Firmware configuration need to be used for interfacing OMAPL137 EMIF-B bus with SRAM (Static RAM) memory devices.

In my understanding.

No.

In OMAPL137, EMIFA is used to interfacing the lower memories and asynchronous whereas EMIFB interfacing is to interface the high speed memories and synchronous.

So, You can use EMIFA for your SRAM interfacing,

Is your SRAM is asynchronous or synchronous ?

Please refer OMAPL137 data sheet page no:86

Any way, I will confirm with team.

Hi Srinivas,

As Titus mentinoned, you can use EMIFA to interface with SRAM. In the TRM the interfacing diagram of EMIFA with asynchronous memories are given at section:20.2.5.1.

Would like to know why would you want to interface the SRAM with EMIFB?

And also in the TRM,  the configuration steps are given for interfacing the EMIFA with Toshiba TC55V16100FT-12 device (ASRAM).( section: 20.3.2.2.3)

Regards,

Shankari

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Hi Titus,

Thank you for the quick reply.

Is your SRAM is asynchronous or synchronous ?

---->It is Asynchronous.

Please let me know if you have any information on this.

Regards
Srinivas

Hi,

Thanks for you inputs. This is about the same requirement mentioned above. One correction, as per one of our requirements we need to interface the EMIF B to SRAM throuh an FPGA, not directly to SRAM.

So FPGA would be interfacing with OMAP - EMIF B from one side, Intrerpret the Read or Write commands and perform the same operation on SRAM on the other side. In one way we can say we are trying to connect Synchronous EMIFB to Asynchronous SRAM through FPGA. FPGA would be acting as Synchronous to Asynchronous bridge.

Yes this would reduce the speeds, but we are ok with the same.

Question is  Can we we write or read only one word from EMIF B.

Please share any application notes available on this topic

PS: Yes we already have the EMIF A interfaced with SRAM and is wroking good.

Thanks in advance.

Santosh Macherla

Hi Srinivas,

Thanks.

I'm repeating the same as Shankari question,

We would like to know why do you want to interface the SRAM with EMIFB?

EMIFA will fulfill your requirement.

Hi,

So FPGA would be interfacing with OMAP - EMIF B from one side, Intrerpret the Read or Write commands and perform the same operation on SRAM on the other side. In one way we can say we are trying to connect Synchronous EMIFB to Asynchronous SRAM through FPGA. FPGA would be acting as Synchronous to Asynchronous bridge.

Okay, Understood.

I will discuss with our hardware experts and will come back soon.

Hi Titus,

Thank you for the reply.

I agree, EMIFA will fulfill the requirement.

But the design/requirement is such a way that I have to use EMFIA for  I/O peripherals and EMFIB for Async SRAM memory.

So i would like to know the EMIFB configuration needed in order to enable this SRAM interface.

Thanks & Regards
Srinivas

Hi Titus,

Sorry to bother you again on this. I appreciate if you can provide inputs on this topic.

Thanks in advance.

Regards
Srinivas

Hi,

I searched a lot of TI links & external to get any sample code for SRAM, but unluckily I found none.

Please refer this link,

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=spra542&fileType=pdf

I will let you know if I found anything relate to SRAM.