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Hyperlink equalization problem C6678

Henry LeBeau
Intellectual 260 points


I've 2 DSP connected via hyperlinks, and the connection seems to be very unstable.

I've configured a 4-lane mode 10GBps connection and  4MB of hyperlink data section is mapped in the shared memory of the other DSP.

The problem is that i have never been able to pass all the 4MB of data to the second DSP.

From the Status Register i've seen that rerror and lerror are both set to 1 (catastrophic failure?|?) and often at this point even the remote access to Hyperlink configuration register in the other device become unaviable.

The point is that i''ve seen a strange set of values in the HyperLink SerDes Status Register  f the 2 DSP: Usually the first DSP to wake up says that all the lanes are underequalized, while the second DSP to wake up says that all lane are OK or that only one lane is under or over equalized. And the 2 DSP are initialized by the same code with the same setting for serdes tx and rx.

It's normal that the 2 DSP sees different status for lane equalization?

Is there any way to optimize the equalization? I've followed the inizialization procedure in SPRUGW8C but there is not written how to manage the equalization problems

  • 0
    TI__Guru* 95265 points

    Can you explain the test HW setup:

    - Is the test with EVM or your customized board?

    - How the cards are connected?

    10 Gb/s may not work, 6.25 Gb should work. lerror and rerror is catastrophic failure.

    What is the SW running on DSP? Can you explain how to see lanes under/overequalized?

    Regards, Eric

  • 0 in reply to lding
    Intellectual 260 points

    I'm using a custom board. The 2 DSP are in the same board and share the same clock 156.25MHz.

    I was using 10Gbps because the errata only says to not use the 12.5Gbps setting

    I'm using a custom firmware and i've seen the lane equalization status reading HyperLink SerDes Status Register

    In my code both DSP sent simultaneously 4 MB of data to the other but only the second to wake up can correctly send the data to the other while the wirst fails

  • 0 in reply to Henry LeBeau
    TI__Guru* 95265 points

    Henry,

    Do you mean the HYPERLINK_SERDES_STS register at 0x02620160 for over/under equalization for each lane? Is the 6.25G working?

    Also, we have noticed that for 10.0G operation, the below MPY for 156.25M ref clock should be 64 instead of 80.

      #if defined(hyplnk_EXAMPLE_REFCLK_156p25)
        #define hyplnk_EXAMPLE_VUSR_PLL_MPY    80 /* MPY i

    There is EQ anaysis code, you may try if help?

    #ifdef hyplnk_EXAMPLE_EQ_ANALYSIS
      hyplnkExampleCheckOneStat (hyplnk_LOCATION_LOCAL, "before eq analysis", 0);
      hyplnkExampleEQAnalysis();
    #endif

    Regards, Eric

  • 0 in reply to lding
    Intellectual 260 points

    Yes, it's the HYPERLINK_SERDES_STS register.

    In my code both DSP sent simultaneously 4 MB of data to the other and check if the data has correctly arrived

    I've tryed the 10gbps operation and definitely does not work.

    The 6.25Gbps operation works usually fine but only for the first DSP that wake up (that says that all the lanes are under-equalized) while the second has never been able to send all data correctly

    The 3.125Gbps work fine for both directions regardless of the order of boot of the 2 DSP but only if thei don't write data simultaneously

  • 0 in reply to Henry LeBeau
    TI__Mastermind 42545 points

    Hi Henry,

    The fact that is operates at lower speeds points towards a layout issue. Can you describe the routing of the Hyperlink between the two DSPs? Be very specific about the trace lengths, trace widths, number of vias, routing layers, position of ground planes and the board materials. 

    Thanks, Bill