Hi guys,
We have a question of EMIF operation frequency on the VC5502 platform. We want to use the EMIF of C5502 through AX88796BLF Ethernet controller chip to send network packets. When we set the PLL frequency on the 300MHz and we got read/write cycle at 1~1.5 µs. We think this is too slow. If we want reduce to 0.1 µs each cycle. How to improve the PLL frequency? Please help provide some suggest to us.
Thank you.
Our EMIF initial register as below:
//Pre-initialized configruation structure for EMIF */
EMIF_Config EmifCfg= {
0x277c, /*GBLCTL1 - EMIF Global Control Register 1 */
0x0009, /*GBLCTL2 - EMIF Global Control Register 2 */
0xff13, /*CE1CTL1 - CE1 Space Control Register 1 */
0xffff, /*CE1CTL2 - CE1 Space Control Register 2 */
0xff13, /*CE0CTL1 - CE0 Space Control Register 1 */
0xffff, /*CE0CTL2 - CE0 Space Control Register 2 */
0xff23, /*CE2CTL1 - CE2 Space Control Register 1 */
0xffff, /*CE2CTL2 - CE2 Space Control Register 2 */
0xff23, /*CE3CTL1 - CE3 Space Control Register 1 */
0xffff, /*CE3CTL2 - CE3 Space Control Register 2 */
0xf000, /*SDCTL1 - SDRAM Control Register 1 */
0x4648, /*SDCTL2 - SDRAM Control Register 2 */
0x1001, /*SDTIM1(SDRFR1)- SDRAM Refresh Control Register 1 */
0x0000, /*SDTIM2(SDRFR2)- SDRAM Refresh Control Register 2 */
0x5f3f, /*SDEXT1 - SDRAM Extension Register 1 */
0x0017, /*SDEXT2 - SDRAM Extension Register 2 */
0x0002, /*CE1SEC1 - CE1 Space Secondary Control Register 1 */
0x0002, /*CE0SEC1 - CE0 Space Secondary Control Register 1 */
0x0002, /*CE2SEC1 - CE2 Space Secondary Control Register 1 */
0x0002, /*CE3SEC1 - CE3 Space Secondary Control Register 1 */
0x0000 /* CESCR - CE Space Size Control Register */ };
.................
//Pre-initialized configuration structure for PLL
PLL_Config PllCfg = {
PLL_PLLCSR_RMK(
PLL_PLLCSR_PLLRST_RESET_ASSERTED,
PLL_PLLCSR_OSCPWRDN_OSC_ON,
PLL_PLLCSR_PLLPWRDN_PLL_ON,
PLL_PLLCSR_PLLEN_DEFAULT ),
0xf, /* PLLM */
0x8000, /* PLLDIV0 -- 300Mhz */
0x8000, /* PLLDIV1 */
0x8001, /* PLLDIV2 -- 150Mhz*/
0x8003, /* PLLDIV3 -- EMIF 75Mhz */
PLL_OSCDIV1_RMK( PLL_OSCDIV1_OD1EN_DISABLED, PLL_OSCDIV1_OSCDIV1_OF(0) ),
