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DM8168 mem_stats.out show M3 req/sec too high

chengwen feng
Prodigy 160 points
Other Parts Discussed in Thread: SYSBIOS

hi, all

    after DM8168 being load ok,  we use mem_stats.out tools to show memory usage,  and we get: 

    it seem that M3 consume too much bandwidth.  we do the following test to find the reason:

a) Is the video-m3/vpss-m3's code/data/stack cacheable ?  

    [result]:  we check the AMMU_m3.cfg,  it already configure cacheable;

b) we force set the video-m3/vpss-m3 in exceptions (by read memory address: 0xffff0000)

    [result]:   M3 req/sec reduce to 0;

c) FAE told us maybe the idle task doing something,  then we execute following code sequence:

    Task_disable();

    for (i = 0; i < 16; i++)

    {
        Hwi_disableInterrupt(i);
    }

    while (1);

    [result]:  the M3 req/sec reduce to 0;

[summarize]:  it seem the some code's raise the problem, can anyone give some tip ?  thanks.

  • 0
    TI__Guru 59700 points

    As mentioned by the FAE the M3 idle loop will do load calculation and also if all tasks are blocked bios will execute a simple counter increment . The M3 cache is configured for write thru so you will see a large number of DR transaction from M3. This number will change when M3 is really loaded. The req/s doesn't reflect the DDR badwidth usage.It only reflect number of DDR requests. The actual DDR bw should be measured using CCS based stats collector module.

  • 0 in reply to Badri Narayanan
    Prodigy 160 points

    Hi, Narayanan

        thanks for your reply,  you are right,  the idle task raise the problem,  yesterday i do the following test: 

        create a task, which priority is 2 (the lowest of all APP's task, but large than idle task),  the task execute following code:

            while (1) {}

        [result]: M3 req/sec reduct to 1.3M req/sec.

    question:

    1. as you say, the idle task do load calculation and simple counter increment,  If we solve the problem by above trick, Is there any further or deeper problem that we haven't see ?

    2. is it possible that :  stop the load calculation and the counter refresh ?  how to config ?

  • 0 in reply to Badri Narayanan
    Prodigy 160 points

    Hi, Narayanan

        is it possible that:  M3 cache configure supporting write back ?

  • 0 in reply to chengwen feng
    TI__Guru 59700 points

    The test you done to have a low priority task in busy loop is a good idea.

    If you want to disable IDLE task comment out

    Hwi.checkStack = FALSE

    and

    use of ti.sysbios.utils.Load module in the BIOS cfg file.

    Ensure that after your change ti_sysbios_knl_Idle_funcList__A is empty in file

    /dvr_rdk/build/dvr_rdk/obj/ti816x-evm/m3vpss/release/dvr_rdk_configuro/package/cfg/MAIN_APP_m3vpss_pem3.c

    This file is generated from the cfg file.

    Also ensure Task.allBlockedFunc is NULL

    To make M3 cache WB_WA refer DVRRDK 4.01. The M3 virtual address memory map is fixed and only certain address range can be marked as WriteBack_WriteAllocate.

    Note that as mentioned before even though you see a large number of requests the actual DDR bw is insignificant and even if there are large number of DDR req/s from m3 it doesn't affect system performance.

  • 0 in reply to Badri Narayanan
    Prodigy 160 points

    Hi, Narayanan

        We config Hwi.checkStackFlag = false,  THEN we get:

    const __T1_ti_sysbios_knl_Idle_funcList ti_sysbios_knl_Idle_funcList__A[1] = {
    ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_sysbios_utils_Load_idleFxn__E)), /* [0] */
    };

        about Load, we already configure: 

    Load.swiEnabled = false;
    Load.hwiEnabled = false;
    Load.taskEnabled = false;
    Load.updateInIdle = false;
    Load.windowInMs = 500;
    Load.postUpdate = '&Utils_prfLoadUpdate';

    Question: How can we remove the "ti_sysbios_utils_Load_idleFxn__E" ?

  • 0 in reply to chengwen feng
    TI__Guru 59700 points

    To comment out Load comment out in file /dvr_rdk/mcfw/src_bios6/cfg/ti816x/BIOS_common.cfg:

    //var Load        = xdc.useModule('ti.sysbios.utils.Load');

    /*

    Load.swiEnabled   = true;
    Load.hwiEnabled   = true;
    Load.taskEnabled  = true;
    Load.updateInIdle = true;
    Load.windowInMs   = 500;
    Load.postUpdate   = '&Utils_prfLoadUpdate';

    */

  • 0 in reply to Badri Narayanan
    Prodigy 160 points

    Hi, Narayanan

        It can't work,  we still have the :

    const __T1_ti_sysbios_knl_Idle_funcList ti_sysbios_knl_Idle_funcList__A[1] = {
    ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_sysbios_utils_Load_idleFxn__E)), /* [0] */
    };

  • 0 in reply to Badri Narayanan
    Prodigy 160 points

    Hi, Narayanan

        here is a question about the M3's L2 SRAM,   DM8168's M3-DUCATI's L2 SRAM size is 256KB,  Does there L2 SRAM can configure as L2 cache ?  If so,  how to config ?

        could you paster a recormanded AMMU_m3.cfg ? 

    thanks.

  • 0 in reply to chengwen feng
    TI__Guru 59700 points

    Ducati L2 cannot be configured  as Cache. Regarding the Load module make sure you have fully disabled use of ti.sysbios.utils.Load in all your cfg files .Also confirm you are not using rta.Agent module which indirectly includes Load module.