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OMAP-L138 Timer Query

tom 121
Prodigy 20 points
Other Parts Discussed in Thread: OMAPL138, OMAP-L138

Hi All,


    I am new to this TI L138. Hope someone will able to assist me in the query below:

    I read from the datasheet (SPRS586H) that there are "Three 64-bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) on page 2. Is all the timer stated usable/meant for the ARM side?

    From OMAPL138_StarterWare_1_10_04_01, i manage to locate the base address as follow:

#define SOC_TMR_0_REGS                      (0x01C20000)
#define SOC_TMR_1_REGS                      (0x01C21000)

#define SOC_TMR_2_REGS                      (0x01F0C000)
#define SOC_TMR_3_REGS                      (0x01F0D000)

   Is the above correct? Should i have 3 or 4 64-bit timer?

Also, i don't seem to be able to locate the above addresses in the Omap-L138 DSP+ARM Processor Technical Reference Manual (spruh77a). Which document will shows the memory-map register and its corresponding bit-field setting function?

Thanks.

Regards,

Tom

  • 0
    TI__Mastermind 43955 points

    Hi Tom,

    I will look into it and get back to you.

    Regards,

    Shankari

  • 0
    TI__Mastermind 43955 points

    Hi Tom,

    Tom says said:
    Also, i don't seem to be able to locate the above addresses in the Omap-L138 DSP+ARM Processor Technical Reference Manual (spruh77a). Which document will shows the memory-map register and its corresponding bit-field setting function?

    In the OMAPL138 Data sheet you will find the memory map for TImer0, 1, 2 and 3.

    There are four 64 bit General purpose timer; each configurable as 32 bit timer as well.  out of four, one can be configured as a watch dog timer (i.e., TIMER1)

    For registers, refer the OMAPl138 TRM.

     

    Regards,

    Shankari

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