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SRIO Error observed during NWRITE_R operation

Aradhana Kumar
Prodigy 30 points

Hi,

I am using TMS320TCi6482 DSP with SRIO as bootloader option. Our software use SRIO NWRITE_R operation to write to another processor (Power Quicc 3). I am using LSU register set 2 for this. Every 20 millisecond, 2 MB of data is pumped through SRIO towards PQ. There is a SRIO switch in between. Sometimes, during the run, I received SRIO error - "Transaction complete, packet not sent due to unsupported transaction type or invalid programming encoding for one or more LSU register fields". I have taken the hexdump of LSU registers but the values found to be correct. I have noticed one thing, though, that this error comes only when software has tried to write 3 bytes of data.

So far, I am not able to figure out the reason for this error. Please help me in finding the cause for this error.

Thanks.

Aradhana

 

  • 0
    TI__Guru* 84110 points

    I suspect you have found the problem already and that it is related to the 3B transfer size in combination with your DSP or SRIO address alignment.

    There was not anything I could find in the User's Guide that explains this clearly, but it mentions combining BYTE_COUNT with SRIO address to form 64b alignment.

    It may be worth your time to try different combinations of BYTE_COUNT and SRIO address alignment to figure out what works and what does not.

  • 0 in reply to RandyP
    Prodigy 30 points

    Thanks Randy.

    Following are the register values at the time of error:

     

    LSU2_REG0: [0x0], LSU2_REG1: [0x3a01fc5c], LSU2_REG2: [0xe6061c5c], LSU2_REG3: [0x3], LSU2_REG4: [0x0], LSU2_REG5: [0xff55], LSU2_REG6: [0x8]

    I am not able to find how 64-bit aligned RIO address is calculated. If we know this then only we'll be able to make appropriate changes to our software.

    Br,

    Aradhana