Hello TI' teams.
I work with custom board developed at company. On board: DM8148 PG3.0 and 2GB of DDR3, 1GB per each EMIF.
We use DDR from Micron – 2 chips MT41K256M16HA-125 per each EMIF (totally 4 DDR' chips on board).
Here DDR' spec: http://www.micron.com/parts/dram/ddr3-sdram/mt41k256m16ha-125
DDR3 tests via JTAG and CCS works fine.
Currently I have a troubles with board bring up.
I tried to load 1-st stage u-boot (in TI' terminology minimal u-boot) via UART to board. "u-boot.min.uart" loaded successfully, but after load completion I don't see prompt.
When connect to the board from Code Composer via JTAG I saw that u-boot hangs in dead loop. Program Counter on address 0x2008Ch. TRM define this dead loop as "Data abort exception default handler" (please see sprugz8d, page 1002 – 4.3.13 "Dead Loops"). From this forum I understand that this dead loop typically occurred when ARM try to access to non-existed memory.
For u-boot I use DM8148 EVM u-boot with my minor modifications corresponds to our DDR timing and LISA configuration.
DMM_LISA configured are as following:
__raw_writel(0x00000000, DMM_LISA_MAP__0);
__raw_writel(0x00000000, DMM_LISA_MAP__1);
__raw_writel(0x80600100, DMM_LISA_MAP__2); // 1GB mapped on SDRC0 only, not interleaved
__raw_writel(0xC0600240, DMM_LISA_MAP__3); // 1GB mapped on SDRC1 only, not interleaved
DRAM configuration defined as is following:
#define PHYS_DRAM_1 0x80000000
#define PHYS_DRAM_2 0xC0000000
#define PHYS_DRAM_1_SIZE 0x40000000
#define PHYS_DRAM_2_SIZE 0x40000000
ARM core registers snapshot by CCS:
=======================================
Core Registers
PC 0x0002008C Program Counter [Core]
SP 0x00000000 General Purpose Register 13 [Core]
LR 0x80705944 General Purpose Register 14 [Core]
CPSR 0x60000197 Stores the status of interrupt enables and critical processor status signals [Core]
R0 0x8070E593 General Purpose Register 0 [Core]
R1 0x00000801 General Purpose Register 1 [Core]
R2 0x00000000 General Purpose Register 2 [Core]
R3 0x8070442C General Purpose Register 3 [Core]
R4 0x8070E58F General Purpose Register 4 [Core]
R5 0x8070E5BC General Purpose Register 5 [Core]
R6 0x00000001 General Purpose Register 6 [Core]
R7 0x00000001 General Purpose Register 7 [Core]
R8 0x80704614 General Purpose Register 8 [Core]
R9 0x8070E5AE General Purpose Register 9 [Core]
R10 0x1A1A1A1A General Purpose Register 10 [Core]
R11 0x00027C94 General Purpose Register 11 [Core]
R12 0x507F853F General Purpose Register 12 [Core]
R13 0x00000000 General Purpose Register 13 [Core]
R14 0x80705944 General Purpose Register 14 [Core]
USER_Registers
R8_USER 0x80704614 General Purpose Register 8 in USER mode [Core]
R9_USER 0x8070E5AE General Purpose Register 9 in USER mode [Core]
R10_USER 0x1A1A1A1A General Purpose Register 10 in USER mode [Core]
R11_USER 0x00027C94 General Purpose Register 11 in USER mode [Core]
R12_USER 0x507F853F General Purpose Register 12 in USER mode [Core]
R13_USER 0x00000000 General Purpose Register 13 in USER mode [Core]
R14_USER 0x00000000 General Purpose Register 14 in USER mode [Core]
FIQ_Registers
SPSR_FIQ 0x00000000 Stores the status of interrupt enables and critical processor status signals [Core]
R8_FIQ 0x014633DC General Purpose Register 8 in FIQ mode [Core]
R9_FIQ 0x8810790F General Purpose Register 9 in FIQ mode [Core]
R10_FIQ 0x10E6343D General Purpose Register 10 in FIQ mode [Core]
R11_FIQ 0x4A6035A4 General Purpose Register 11 in FIQ mode [Core]
R12_FIQ 0x080D00D8 General Purpose Register 12 in FIQ mode [Core]
R13_FIQ 0x00000000 General Purpose Register 13 in FIQ mode [Core]
R14_FIQ 0x00000000 General Purpose Register 14 in FIQ mode [Core]
Supervisor_Registers
SPSR_SVC 0x00000000 Stores the status of interrupt enables and critical processor status signals in supervisor mode [Core]
R13_SVC 0x806FDB70 General Purpose Register 13 in Supervisor mode [Core]
R14_SVC 0x8070051C General Purpose Register 14 in Supervisor mode [Core]
I would be very grateful if you could help me fix the problem. (possible correct my wrong LISA setting?).
ThanX alot.
