My config: using TM4C1294NCPDT eval kit, CCS v6.0, TI-RTOS 2.0.1.23, SysBios 6.40.01.15, Compiler TI v5.1.5
I am trying to break up my FLASH space between 1/4 bootloader - 3/4 application. The bootloader will be initially programmed at address 0x0000.0000 and the application will be flashed via the bootloader at address 0x0004.0000. Are these the correct settings?:
the application's TM4C1294NCPDT.cmd file:
--retain=g_pfnVectors
#define BL_BASE 0x00000000
#define APP_BASE 0x00040000
#define APP_NVEC 0x00040400
#define RAM_BASE 0x20000000
MEMORY
{
FLASH_BL (RX) : origin = BL_BASE, length = 0x00040000
FLASH_VEC (RX) : origin = APP_BASE, length = 0x00000400
FLASH (RX) : origin = APP_NVEC, length = 0x000BFC00
SRAM (RWX) : origin = RAM_BASE, length = 0x00040000
}
SECTIONS
{
.intvecs: > APP_BASE
.text : > FLASH
.const : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH
.vtable : > RAM_BASE
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM
}
__STACK_TOP = __stack + 512;
I still see the .resetVecs at address 0x0000.0000 in the resulting application's .map file. I did try adding these lines to the application's TI RTOS .cfg file:
Program.sectMap[".resetVecs"] = new Program.SectionSpec(); Program.sectMap[".resetVecs"] = "FLASH_VEC";
but I got the same results. What else do I need to change to ensure everything is setup for the application to run only in its FLASH space? NOTE: both bootloader and application will use TI RTOS.