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NFS root file system SDK 07 (DHCP/BOOTP: Reply not for us)

Santhosh Ramani
Expert 2765 points

Hello Guys,

I'm trying to get NFS root file system to work and facing this issue. Uboot picks up the kernel and device tree binary from TFTP server on my linux machine. I've set the NFS root file system on my machine as well. But the system fails to receive an ip address with DHCP.

The final few steps of the boot process are below:

[ 3.311612] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[ 3.318136] davinci_mdio 4a101000.mdio: detected phy mask fffffffd
[ 3.325945] libphy: 4a101000.mdio: probed
[ 3.330256] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver unknown
[ 3.343711] Detected MACID = 1c:ba:8c:c4:b6:78
[ 3.351817] omap_rtc 44e3e000.rtc: setting system clock to 2000-01-01 00:57:52 UTC (946688272)
[ 3.367795] net eth0: initializing cpsw version 1.12 (0)
[ 3.376184] net eth0: phy found : id is : 0x20005c90
[ 3.389594] 8021q: adding VLAN 0 to HW filter on device eth0
[ 5.372227] libphy: 4a101000.mdio:01 - Link is Up - 100/Full
[ 5.391619] Sending DHCP requests .....[ 35.080309] DHCP/BOOTP: Reply not for us, op[2] xid[c362e7ad]
.[ 60.482376] PM: request_firmware failed

All your help is much appreciated.

Thank you

Regards

Santhosh

  • 0
    TI__Mastermind 25235 points

    Hi Santosh,

    Please check your dhcp server about any log messages from this moment that may suggest what could be wrong.

    Please also post the kernel bootargs here.

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    Expert 2765 points

    Hello Miroslav,

    I am not able to check the dhcp server log messages as I'm hooking it up to our internal network. I should add the following information:

    I am able to boot with TFTP using the same scheme.

    I am able to boot with TFTP and use NFS root file system using SDK 06 release.

    I am attaching the boot log starting from Uboot so you can see that Uboot is able to get ip address using DHCP. The kernel bootargs are as follows:

    Kernel command line: console=ttyO0,115200n8 root=/dev/nfs nfsroot=192.168.2.4:/home/sramani/aatargetNFS,nolock rw ip=dhcp


    The /etc/exports file looks like this

    /home/sramani/aatargetNFS *(rw,sync,no_root_squash,no_subtree_check)


    If there is a way to check the log messages from DHCP server, then please let me know.

    Thank you for your help.

    Regards

     

    Santhosh

    Fullscreen 1817.nfs_boot.log Download 
    =~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2014.06.12 08:53:45 =~=~=~=~=~=~=~=~=~=~=~=


U-Boot SPL 2013.10-00189-g78d8ebd-dirty (Jun 11 2014 - 18:47:29)
*** SR: I2C initialization is complete ***
*** SR: get_dpll_ddr_params is complete ***
*** SR: Setup MMC0 pin mux ***
*** SR: Setup NAND pin mux ***
*** SR: Setup MII1 (ethernet) pin mux ***
*** SR: set_mux_conf_regs is complete ***
*** AA: DDR Frequency is 166 Mhz ***

*** SR: Entering am33xx_spl_board_init ***
*** SR: DCDC1 - 1.8V ***
*** SR: DCDC2 - 3.3V ***
*** SR: DCDC3 - 1.1V ***
*** SR: LDO1  - 1.8V ***
*** SR: LDO2  - 3.3V ***
*** AA: Operating Performance Point is OPP100  ***
*** AA: MPU Frequency is 300 Mhz ***
*** SR: am33xx_spl_board_init is complete ***
reading u-boot.img
reading u-boot.img


U-Boot 2013.10-00189-g78d8ebd-dirty (Jun 11 2014 - 18:47:29)

I2C:   ready
DRAM:  128 MiB
NAND:  256 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment

Net:   <ethaddr> not set. Validating first E-fuse MAC

*** SR: board_eth_init is complete ***
cpsw
Hit any key to stop autoboot:  3  2  1  0 
U-Boot# run srboot


Booting from sramani tftp server ...
serverip=192.168.2.4
NFS server set to sramani ...
rootpath=/home/sramani/aatargetNFS
Booting from network ...
link up on port 0, speed 100, full duplex
BOOTP broadcast 1
DHCP client bound to address 192.168.2.69
link up on port 0, speed 100, full duplex
Using cpsw device
TFTP from server 192.168.2.4; our IP address is 192.168.2.69
Filename 'zImage'.
Load address: 0x80200000
Loading: *#################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 #####################################
 955.1 KiB/s
done
Bytes transferred = 3512472 (359898 hex)
link up on port 0, speed 100, full duplex
Using cpsw device
TFTP from server 192.168.2.4; our IP address is 192.168.2.69
Filename 'aa-hcc.dtb'.
Load address: 0x80f80000
Loading: *########
 789.1 KiB/s
done
Bytes transferred = 37173 (9135 hex)
Kernel image @ 0x80200000 [ 0x000000 - 0x359898 ]
## Flattened Device Tree blob at 80f80000
   Booting using the fdt blob at 0x80f80000
   Loading Device Tree to 87b2e000, end 87b3a134 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.12.10-ti2013.12.01 (sramani@sr) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #6 Wed Jun 11 19:49:32 CDT 2014
[    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine: Generic AM33XX (Flattened Device Tree), model: AA Home Comfort Control
[    0.000000] cma: CMA: reserved 24 MiB at 86000000
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] CPU: All CPU(s) started in SVC mode.
[    0.000000] AM335X ES2.1 (neon )
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 31744
[    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs nfsroot=192.168.2.4:/home/sramani/aatargetNFS,nolock rw ip=dhcp
[    0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Memory: 94900K/128000K available (4715K kernel code, 418K rwdata, 1556K rodata, 269K init, 201K bss, 33100K reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xc8800000 - 0xff000000   ( 872 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xc8000000   ( 128 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0628004   (6273 kB)
[    0.000000]       .init : 0xc0629000 - 0xc066c464   ( 270 kB)
[    0.000000]       .data : 0xc066e000 - 0xc06d6958   ( 419 kB)
[    0.000000]        .bss : 0xc06d6958 - 0xc0708e80   ( 202 kB)
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
[    0.000000] Total of 128 interrupts on 1 active controller
[    0.000000] OMAP clockevent source: timer2 at 25000000 Hz
[    0.000000] sched_clock: 32 bits at 25MHz, resolution 40ns, wraps every 171798ms
[    0.000000] OMAP clocksource: timer1 at 25000000 Hz
[    0.000000] Console: colour dummy device 80x30
[    0.000638] Calibrating delay loop... 199.06 BogoMIPS (lpj=995328)
[    0.069380] pid_max: default: 32768 minimum: 301
[    0.069577] Security Framework initialized
[    0.069750] Mount-cache hash table entries: 512
[    0.088405] CPU: Testing write buffer coherency: ok
[    0.089143] Setting up static identity map for 0xc04a1128 - 0xc04a1198
[    0.096352] devtmpfs: initialized
[    0.100393] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
[    0.174534] omap_hwmod: debugss: _wait_target_disable failed
[    0.175898] pinctrl core: initialized pinctrl subsystem
[    0.177748] regulator-dummy: no parameters
[    0.182369] NET: Registered protocol family 16
[    0.187273] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.192395] cpuidle: using governor ladder
[    0.192429] cpuidle: using governor menu
[    0.213115] platform mpu.1: FIXME: clock-name 'fck' DOES NOT exist in dt!
[    0.215654] platform 49000000.edma: FIXME: clock-name 'fck' DOES NOT exist in dt!
[    0.218437] OMAP GPIO hardware version 0.1
[    0.240297] omap-gpmc 50000000.gpmc: could not find pctldev for node /pinmux@44e10800/nandflash_pins_default, deferring probe
[    0.240362] platform 50000000.gpmc: Driver omap-gpmc requests probe deferral
[    0.241327] platform 56000000.sgx: FIXME: clock-name 'fck' DOES NOT exist in dt!
[    0.246505] DSS not supported on this SoC
[    0.246539] No ATAGs?
[    0.246563] hw-breakpoint: debug architecture 0x4 unsupported.
[    0.296550] bio: create slab <bio-0> at 0
[    0.332610] edma-dma-engine edma-dma-engine.0: TI EDMA DMA engine driver
[    0.334478] vmmcsd_fixed: 3300 mV 
[    0.340356] SCSI subsystem initialized
[    0.342224] usbcore: registered new interface driver usbfs
[    0.342666] usbcore: registered new interface driver hub
[    0.343149] usbcore: registered new device driver usb
[    0.345173] omap_i2c 44e0b000.i2c: could not find pctldev for node /pinmux@44e10800/pinmux_i2c0_pins, deferring probe
[    0.345234] platform 44e0b000.i2c: Driver omap_i2c requests probe deferral
[    0.345294] omap_i2c 4819c000.i2c: could not find pctldev for node /pinmux@44e10800/pinmux_i2c2_pins, deferring probe
[    0.345331] platform 4819c000.i2c: Driver omap_i2c requests probe deferral
[    0.346152] pps_core: LinuxPPS API ver. 1 registered
[    0.346179] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.346495] PTP clock support registered
[    0.351521] Switched to clocksource timer1
[    0.397647] NET: Registered protocol family 2
[    0.399051] TCP established hash table entries: 1024 (order: 1, 8192 bytes)
[    0.399132] TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
[    0.399180] TCP: Hash tables configured (established 1024 bind 1024)
[    0.399350] TCP: reno registered
[    0.399384] UDP hash table entries: 256 (order: 0, 4096 bytes)
[    0.399431] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[    0.399881] NET: Registered protocol family 1
[    0.400635] RPC: Registered named UNIX socket transport module.
[    0.400660] RPC: Registered udp transport module.
[    0.400676] RPC: Registered tcp transport module.
[    0.400692] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.402522] NetWinder Floating Point Emulator V0.97 (double precision)
[    0.403813] PM: Loading am335x-pm-firmware.bin
[    0.709064] VFS: Disk quotas dquot_6.5.2
[    0.709207] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.710419] NFS: Registering the id_resolver key type
[    0.710583] Key type id_resolver registered
[    0.710605] Key type id_legacy registered
[    0.710729] msgmni has been set to 233
[    0.714499] NET: Registered protocol family 38
[    0.714593] io scheduler noop registered
[    0.714613] io scheduler deadline registered
[    0.714657] io scheduler cfq registered (default)
[    0.718656] pinctrl-single 44e10800.pinmux: 142 pins at pa f9e10800 size 568
[    0.791890] Console: switching to colour frame buffer device 100x30
[    0.807643] 44e09000.serial: ttyO0 at MMIO 0x44e09000 (irq = 88, base_baud = 3000000) is a OMAP UART0
[    1.427886] console [ttyO0] enabled
[    1.433496] 48022000.serial: ttyO1 at MMIO 0x48022000 (irq = 89, base_baud = 3000000) is a OMAP UART1
[    1.446322] omap_rng 48310000.rng: OMAP Random Number Generator ver. 20
[    1.478164] brd: module loaded
[    1.494426] loop: module loaded
[    1.505145] mtdoops: mtd device (mtddev=name/number) must be supplied
[    1.517113] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    1.524270] ehci-omap: OMAP-EHCI Host Controller driver
[    1.530839] usbcore: registered new interface driver usb-storage
[    1.540251] mousedev: PS/2 mouse device common for all mice
[    1.548317] input: ti-tsc as /devices/ocp.2/44e0d000.tscadc/TI-am335x-tsc/input/input0
[    1.559984] omap_rtc 44e3e000.rtc: rtc core: registered 44e3e000.rtc as rtc0
[    1.567750] 44e3e000.rtc: already running
[    1.573065] i2c /dev entries driver
[    1.580239] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[    1.591106] edma-dma-engine edma-dma-engine.0: allocated channel for 0:25
[    1.598753] edma-dma-engine edma-dma-engine.0: allocated channel for 0:24
[    1.643962] edma-dma-engine edma-dma-engine.0: allocated channel for 0:36
[    1.651333] omap-sham 53100000.sham: hw accel on OMAP rev 4.3
[    1.660223] omap-aes 53500000.aes: OMAP AES hw accel rev: 3.2
[    1.666624] edma-dma-engine edma-dma-engine.0: allocated channel for 0:5
[    1.673833] edma-dma-engine edma-dma-engine.0: allocated channel for 0:6
[    1.683983] usbcore: registered new interface driver usbhid
[    1.689915] usbhid: USB HID core driver
[    1.698139] oprofile: no performance counters
[    1.703804] oprofile: using timer interrupt.
[    1.709000] TCP: cubic registered
[    1.712610] Initializing XFRM netlink socket
[    1.717296] NET: Registered protocol family 17
[    1.722163] NET: Registered protocol family 15
[    1.726996] 8021q: 802.1Q VLAN Support v1.8
[    1.731651] Key type dns_resolver registered
[    1.737369] cpu cpu0: cpu0 regulator not ready, retry
[    1.743113] platform cpufreq-cpu0.0: Driver cpufreq-cpu0 requests probe deferral
[    1.752142] ThumbEE CPU extension supported.
[    1.760817] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    1.766446] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    1.774931] ONFI param page 0 valid
[    1.778666] ONFI flash detected
[    1.782136] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAH4), 256MiB, page size: 2048, OOB size: 64
[    1.794299] omap2-nand: detected x8 NAND flash
[    1.799026] nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme
[    1.804756] omap2-nand: using custom ecc layout
[    1.809964] 10 ofpart partitions found on MTD device omap2-nand.0
[    1.816500] Creating 10 MTD partitions on "omap2-nand.0":
[    1.822304] 0x000000000000-0x000000020000 : "NAND.SPL"
[    1.831506] 0x000000020000-0x000000040000 : "NAND.SPL.backup1"
[    1.841262] 0x000000040000-0x000000060000 : "NAND.SPL.backup2"
[    1.850661] 0x000000060000-0x000000080000 : "NAND.SPL.backup3"
[    1.860154] 0x000000080000-0x0000000c0000 : "NAND.u-boot-spl-os"
[    1.869941] 0x0000000c0000-0x0000001c0000 : "NAND.u-boot"
[    1.879695] 0x0000001c0000-0x0000001e0000 : "NAND.u-boot-env"
[    1.889210] 0x0000001e0000-0x000000200000 : "NAND.u-boot-env.backup1"
[    1.899477] 0x000000200000-0x000000a00000 : "NAND.kernel"
[    1.915504] 0x000000a00000-0x000010000000 : "NAND.file-system"
[    2.144879] vdds_ddr: 1800 mV 
[    2.151127] vdd_peripheral: 3300 mV 
[    2.157912] vdd_mpu: 1100 mV 
[    2.163332] LDO1: 1800 mV 
[    2.168382] LDO2: 3300 mV 
[    2.172397] LDO3: at 1800 mV 
[    2.176638] LDO4: at 2800 mV 
[    2.181028] tps65217 0-0024: TPS65217 ID 0x7 version 1.2
[    2.186799] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
[    2.196905] sht21 2-0040: initialized
[    2.201985] rtc-pcf8563 2-0051: chip found, driver version 0.4.3
[    3.201561] omap_i2c 4819c000.i2c: controller timed out
[    3.221570] rtc-pcf8563 2-0051: pcf8563_get_datetime: read error
[    3.228775] rtc-pcf8563 2-0051: rtc core: registered rtc-pcf8563 as rtc1
[    3.236126] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 400 kHz
[    3.311611] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[    3.318137] davinci_mdio 4a101000.mdio: detected phy mask fffffffd
[    3.325887] libphy: 4a101000.mdio: probed
[    3.330199] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver unknown
[    3.340015] SR: Value of phyid = 1
[    3.343630] Detected MACID = 1c:ba:8c:c4:b6:78
[    3.351719] omap_rtc 44e3e000.rtc: setting system clock to 2000-01-01 00:00:38 UTC (946684838)
[    3.367694] net eth0: initializing cpsw version 1.12 (0)
[    3.376065] net eth0: phy found : id is : 0x20005c90
[    3.389462] 8021q: adding VLAN 0 to HW filter on device eth0
[    5.372240] libphy: 4a101000.mdio:01 - Link is Up - 100/Full
[    5.391613] Sending DHCP requests ....[   28.700456] DHCP/BOOTP: Reply not for us, op[2] xid[5dcfa448]
.[   54.726030] DHCP/BOOTP: Reply not for us, op[2] xid[e2f75c69]


     

  • 0 in reply to Santhosh Ramani
    TI__Mastermind 25235 points

    Santosh,

    The log from the DHCP server, if enabled at all, can be monitored on the server machine itself. However, I can't help you with this as there are different DHCP servers which probably store the log files in different places.

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    Expert 2765 points

    Hello Miroslav,

    I understand the DHCP server issue - but I don't think it's a DHCP server problem. As I said, SDK  06 version works perfectly fine. I think the problem is with the Linux kernel setting - uboot is able to get an address from the DHCP server.

    Is there a particular log or setting information that you need from me to help me diagnose the problem.

    Thank you

    Regards

    Santhosh

  • 0 in reply to Santhosh Ramani
    TI__Mastermind 25235 points

    Santosh,

    I'm testing this with stock SDK v7 on the AM335x GP EVM board and everything works correctly:

    U-Boot# setenv rootpath /home/users/mkiradzhiyski/ti-sdk-am335x-evm-07.00.00.00/targetNFS
    U-Boot# setenv serverip 172.20.1.57
    U-Boot# setenv bootfile zImage-am335x-evm.bin
    U-Boot# setenv fdtfile am335x-evm.dtb
    U-Boot# run netboot
    Booting from network ...
    link up on port 0, speed 100, full duplex
    BOOTP broadcast 1
    DHCP client bound to address 172.20.2.162
    link up on port 0, speed 100, full duplex
    Using cpsw device
    TFTP from server 172.20.1.57; our IP address is 172.20.2.162

    ..........

    [    4.390890] Sending DHCP requests ., OK
    [    4.481360] IP-Config: Got DHCP answer from 172.20.0.1, my address is 172.20.2.162
    [    4.489637] IP-Config: Complete:
    [    4.493088]      device=eth0, hwaddr=00:18:31:e2:5f:29, ipaddr=172.20.2.162, mask=255.255.0.0, gw=172.20.0.1
    [    4.503487]      host=172.20.2.162, domain=int.mm-sol.com, nis-domain=(none)
    [    4.511001]      bootserver=0.0.0.0, rootserver=172.20.1.57, rootpath=
    [    4.517718]      nameserver0=172.20.0.1, nameserver1=172.18.0.1
    [    4.570199] VFS: Mounted root (nfs filesystem) on device 0:13.
    [    4.576875] devtmpfs: mounted
    [    4.580616] Freeing unused kernel memory: 344K (c074b000 - c07a1000)
    INIT: version 2.88 booting

    ..........

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    Expert 2765 points

    Hello Miroslav,


    Here is what I tested - I took the dtb file that is native to my board and used the zImage from the pre-built images. Based on that I still ran into the same issue - so that tells me that there is something wrong with my dts file. Can you confirm this?

    I'm attaching my dts file - please let me know if you see anything out of the ordinary.  I think the connection to the phy is working properly - as uboot is able to perform tftpboot....but Linux kernel doesn't seem to be able to get connection to the outside world.


    I do get the following messages:

    [    2.505513] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
    [    2.512025] davinci_mdio 4a101000.mdio: detected phy mask fffffffd
    [    2.519869] libphy: 4a101000.mdio: probed
    [    2.524166] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver unknown
    [    2.534246] Detected MACID = 1c:ba:8c:c4:b6:78
    [    2.542813] omap_rtc 44e3e000.rtc: setting system clock to 2000-01-01 00:02:59 UTC (946684979)
    [    2.559020] net eth0: initializing cpsw version 1.12 (0)
    [    2.567319] net eth0: phy found : id is : 0x20005c90
    [    2.580727] 8021q: adding VLAN 0 to HW filter on device eth0
    [    4.566160] libphy: 4a101000.mdio:01 - Link is Up - 100/Full

    Hence my conclusion that something is not correct in my linux device tree setup.

    Please let me know your thoughts.


    - Santhosh

    Fullscreen 4527.dts_file.txt Download 
    /*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "am33xx.dtsi"

/ {
	model = "AA Home Comfort Control";
	compatible = "AA, HCC", "ti,am33xx";

	cpus {
		cpu@0 {
			cpu0-supply = <&dcdc3_reg>;	/* Refer to the TPS65217 section */
		};
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x8000000>;	/* 128 MB */
	};

	am33xx_pinmux: pinmux@44e10800 {
		pinctrl-names = "default";		
	
		/*
		 * The following definitions are for the PIN mux values. Each GPIO pad has a control
		 * register that sets up the mode of operation along with other options (see Control Module)
		 * The offset for the GPIO pads start at 0x800. Each GPIO pin shown below is an offset from 
		 * that address. 
		 * For eg: An address of 0x188 is actually 0x988 ==> conf_i2c0_sda
		 *
		 * Tip: Use the uboot mux.c file for reference
		 */
		
		i2c0_pins: pinmux_i2c0_pins {
			pinctrl-single,pins = <
				0x188 (PIN_INPUT | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
				0x18c (PIN_INPUT | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
			>;
		};

		i2c2_pins: pinmux_i2c2_pins {
			pinctrl-single,pins = <
				0x178 (PIN_INPUT | MUX_MODE2)	/* uart1_ctsn.i2c2_sda */
				0x17C (PIN_INPUT | MUX_MODE2)	/* uart1_rtsn.i2c2_scl */
			>;
		};

		uart0_pins: pinmux_uart0_pins {
			pinctrl-single,pins = <
				0x170 (PIN_INPUT_PULLUP		| MUX_MODE0)	/* uart0_rxd.uart0_rxd */
				0x174 (PIN_OUTPUT_PULLDOWN	| MUX_MODE0)	/* uart0_txd.uart0_txd */
			>;
		};
		
		
		/* 
			The following are definitions for the support Module (UART-4) tbd
		 */
		uart1_pins_default: pinmux_uart1_pins_default {
			pinctrl-single,pins = <
				0x180 (PIN_INPUT_PULLUP | MUX_MODE0)		/* uart1_rxd.uart1_rxd */
				0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) 	/* uart1_txd.uart1_txd */
			>;
		};

		uart1_pins_sleep: pinmux_uart1_pins_sleep {
			pinctrl-single,pins = <
				0x180 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			>;
		};

		
		/*
			The following are the NAND Inteface signals (Standard no change)
		*/
		nandflash_pins_default: nandflash_pins_default {
			pinctrl-single,pins = <
				0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
				0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
				0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
				0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
				0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
				0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
				0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
				0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
				0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
				0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
				0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
				0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
				0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
				0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
				0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
			>;
		};

		nandflash_pins_sleep: nandflash_pins_sleep {
			pinctrl-single,pins = <
				0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			>;
		};
		
		/*
			The following definitions are for the LCD Backlight
		*/
		ecap0_pins_default: backlight_pins {
			pinctrl-single,pins = <
				0x164 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
			>;
		};

		ecap0_pins_sleep: ecap0_pins_sleep {
			pinctrl-single,pins = <
				0x164  (PULL_DISABLE | MUX_MODE7)		/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
			>;
		};
		
		
		/*
			The following definitions are for the MII interface used for wired ethernet
			We use the MII interface without Gigabit Ethernet and only have 1 slave PHY
			NOTE - Removed all pull-up and pull-down from input signals
			
			We are using DP83848I - for this, the following settings are best. There are
			pull-up requirements on the PHY (so make sure these are not conflicting)
		*/
		cpsw_default: cpsw_default {
			pinctrl-single,pins = <
				/* Slave 1 */
				0x108 (PIN_INPUT  | MUX_MODE0)			/* mii1_col */
				0x10c (PIN_INPUT  | MUX_MODE0)			/* mii1_crs */
				0x110 (PIN_INPUT  | MUX_MODE0)			/* mii1_rxer */
				0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txen */
				0x118 (PIN_INPUT  | MUX_MODE0)			/* mii1_rxdv */
				0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd3 */
				0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd2 */
				0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd1 */
				0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd0 */
				0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txclk */
				0x130 (PIN_INPUT  | MUX_MODE0)			/* mii1_rxclk */
				0x134 (PIN_INPUT  | MUX_MODE0)			/* mii1_rxd3 */
				0x138 (PIN_INPUT  | MUX_MODE0)			/* mii1_rxd2 */
				0x13c (PIN_INPUT  | MUX_MODE0)			/* mii1_rxd1 */
				0x140 (PIN_INPUT  | MUX_MODE0)			/* mii1_rxd0 */
			>;
		};

		cpsw_sleep: cpsw_sleep {
			pinctrl-single,pins = <
				/* Slave 1 reset value */
				0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			>;
		};
		
		/*
			NOTE - Removed pull-up from the MDIO as there is a hard pull-up on the board
		*/	
		davinci_mdio_default: davinci_mdio_default {
			pinctrl-single,pins = <
				/* MDIO */
				0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)			/* mdio_data.mdio_data */
				0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)					/* mdio_clk.mdio_clk */
			>;
		};

		davinci_mdio_sleep: davinci_mdio_sleep {
			pinctrl-single,pins = <
				/* MDIO reset value */
				0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			>;
		};
		
		/*
			The following definitions are for MMC-0 (We use GPIO_0_29 as
			the card detect). There is no write protect signal. [MODE 7 is normal GPIO]
		*/
		mmc1_pins_default: pinmux_mmc1_pins {
			pinctrl-single,pins = <
				0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3.mmc0_dat3 */
				0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat2.mmc0_dat2 */
				0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat1.mmc0_dat1 */
				0x0FC (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat0.mmc0_dat0 */
				0x100 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_clk.mmc0_clk */
				0x104 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_cmd.mmc0_cmd */
				0x144 (PIN_INPUT | MUX_MODE7)			/* rmii1_ref_clk.gpio0_29 */
			>;
		};

		mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
			pinctrl-single,pins = <
				0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
				0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			>;
		};
		
		/*
			The following definitions are for LCD signals (we use 24 bpp)
		*/		
		lcd_pins_default: lcd_pins_default {
			pinctrl-single,pins = <
				0x20 0x01	/* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
				0x24 0x01	/* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
				0x28 0x01	/* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
				0x2c 0x01	/* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
				0x30 0x01	/* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
				0x34 0x01	/* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
				0x38 0x01	/* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
				0x3c 0x01	/* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
				0xa0 0x00	/* lcd_data0.lcd_data0, OUTPUT | MODE0 */
				0xa4 0x00	/* lcd_data1.lcd_data1, OUTPUT | MODE0 */
				0xa8 0x00	/* lcd_data2.lcd_data2, OUTPUT | MODE0 */
				0xac 0x00	/* lcd_data3.lcd_data3, OUTPUT | MODE0 */
				0xb0 0x00	/* lcd_data4.lcd_data4, OUTPUT | MODE0 */
				0xb4 0x00	/* lcd_data5.lcd_data5, OUTPUT | MODE0 */
				0xb8 0x00	/* lcd_data6.lcd_data6, OUTPUT | MODE0 */
				0xbc 0x00	/* lcd_data7.lcd_data7, OUTPUT | MODE0 */
				0xc0 0x00	/* lcd_data8.lcd_data8, OUTPUT | MODE0 */
				0xc4 0x00	/* lcd_data9.lcd_data9, OUTPUT | MODE0 */
				0xc8 0x00	/* lcd_data10.lcd_data10, OUTPUT | MODE0 */
				0xcc 0x00	/* lcd_data11.lcd_data11, OUTPUT | MODE0 */
				0xd0 0x00	/* lcd_data12.lcd_data12, OUTPUT | MODE0 */
				0xd4 0x00	/* lcd_data13.lcd_data13, OUTPUT | MODE0 */
				0xd8 0x00	/* lcd_data14.lcd_data14, OUTPUT | MODE0 */
				0xdc 0x00	/* lcd_data15.lcd_data15, OUTPUT | MODE0 */
				0xe0 0x00	/* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
				0xe4 0x00	/* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
				0xe8 0x00	/* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
				0xec 0x00	/* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
			>;
		};

		lcd_pins_sleep: lcd_pins_sleep {
			pinctrl-single,pins = <
				0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad8.lcd_data16 */
				0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad9.lcd_data17 */
				0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad10.lcd_data18 */
				0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad11.lcd_data19 */
				0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad12.lcd_data20 */
				0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad13.lcd_data21 */
				0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad14.lcd_data22 */
				0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad15.lcd_data23 */
				0xa0 (PULL_DISABLE | MUX_MODE7)		/* lcd_data0.lcd_data0 */
				0xa4 (PULL_DISABLE | MUX_MODE7)		/* lcd_data1.lcd_data1 */
				0xa8 (PULL_DISABLE | MUX_MODE7)		/* lcd_data2.lcd_data2 */
				0xac (PULL_DISABLE | MUX_MODE7)		/* lcd_data3.lcd_data3 */
				0xb0 (PULL_DISABLE | MUX_MODE7)		/* lcd_data4.lcd_data4 */
				0xb4 (PULL_DISABLE | MUX_MODE7)		/* lcd_data5.lcd_data5 */
				0xb8 (PULL_DISABLE | MUX_MODE7)		/* lcd_data6.lcd_data6 */
				0xbc (PULL_DISABLE | MUX_MODE7)		/* lcd_data7.lcd_data7 */
				0xc0 (PULL_DISABLE | MUX_MODE7)		/* lcd_data8.lcd_data8 */
				0xc4 (PULL_DISABLE | MUX_MODE7)		/* lcd_data9.lcd_data9 */
				0xc8 (PULL_DISABLE | MUX_MODE7)		/* lcd_data10.lcd_data10 */
				0xcc (PULL_DISABLE | MUX_MODE7)		/* lcd_data11.lcd_data11 */
				0xd0 (PULL_DISABLE | MUX_MODE7)		/* lcd_data12.lcd_data12 */
				0xd4 (PULL_DISABLE | MUX_MODE7)		/* lcd_data13.lcd_data13 */
				0xd8 (PULL_DISABLE | MUX_MODE7)		/* lcd_data14.lcd_data14 */
				0xdc (PULL_DISABLE | MUX_MODE7)		/* lcd_data15.lcd_data15 */
				0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
				0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_hsync.lcd_hsync */
				0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_pclk.lcd_pclk */
				0xec (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_ac_bias_en.lcd_ac_bias_en */
			>;
		};
	};

	ocp {
		uart0: serial@44e09000 {
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pins>;

			status = "okay";
		};

		uart1: serial@48022000 {
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart1_pins_default>;
			pinctrl-1 = <&uart1_pins_sleep>;

			status = "okay";
		};

		i2c0: i2c@44e0b000 {
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pins>;
			status = "okay";
			clock-frequency = <400000>;
			
			/* Set OPP100 (1.10V) for VDD core */
			sleep-sequence = /bits/ 8 <
				0x02 0x24 0x0b 0x6d /* Password unlock 1 */
				0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */
				0x02 0x24 0x0b 0x6d /* Password unlock 2 */
				0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */
				0x02 0x24 0x0b 0x6c /* Password unlock 1 */
				0x02 0x24 0x11 0x86 /* Apply DCDC changes */
				0x02 0x24 0x0b 0x6c /* Password unlock 2 */
				0x02 0x24 0x11 0x86 /* Apply DCDC changes */
			>;

			/* Set OPP100 (1.10V) for VDD core */
			wake-sequence = /bits/ 8 <
				0x02 0x24 0x0b 0x6d /* Password unlock 1 */
				0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */
				0x02 0x24 0x0b 0x6d /* Password unlock 2 */
				0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */
				0x02 0x24 0x0b 0x6c /* Password unlock 1 */
				0x02 0x24 0x11 0x86 /* Apply DCDC changes */
				0x02 0x24 0x0b 0x6c /* Password unlock 2 */
				0x02 0x24 0x11 0x86 /* Apply DCDC changes */
			>;

			tps: tps@24 {
				reg = <0x24>;
			};
		};
		
		
		/* 
			The following are the USB settings. We only have 1 USB (0) and 
			is used as a Host
		 */
		musb: usb@47400000 {		/* USB Susbsystem registers */
			status = "okay";

			control@44e10000 {		/* Control Module registers */		
				status = "okay";
			};

			usb-phy@47401300 {		/* USB-0 PHY registers */
				status = "okay";
			};

			usb@47401000 {			/* USB-0 Controller registers */
				status = "okay";
				dr_mode = "host";
			};
			
			dma-controller@07402000  {
				status = "okay";
			};
		};
		
		
		/* 
			The following are the I2C-2 settings. We have 2 devices set-up on the
			I2C-2 bus - SHT21 and RTC PCF8563
		 */
		i2c2: i2c@4819c000 {
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_pins>;

			status = "okay";
			clock-frequency = <400000>;		
			
			/* Address is 0x80 (but entered as 0x80 >> 1) */
			sht21: sht21@40 {
				compatible = "Sensirion,sht21";
				reg = <0x40>;
			};
			
			/* Address is 0xA2 (but entered as 0xA2 >> 1) */	
			pcf8563: pcf8563@51 {
				compatible = "NXP,pcf8563";
				reg = <0x51>;
			};
		};
		
		
		
		elm: elm@48080000 {
			status = "okay";
		};
		
		
		/* 
			The following are the PWM settings for the LCD Backlight
		 */
		epwmss0: epwmss@48300000 {
			status = "okay";

			ecap0: ecap@48300100 {
				status = "okay";
				pinctrl-names = "default", "sleep";
				pinctrl-0 = <&ecap0_pins_default>;
				pinctrl-1 = <&ecap0_pins_sleep>;
			};
		};
		
		/* 
			The following are the GPMC (NAND) settings. 2GB NAND
			TODO - come back to this later
		 */
		gpmc: gpmc@50000000 {
			status = "okay";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&nandflash_pins_default>;
			pinctrl-1 = <&nandflash_pins_sleep>;
			ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND, 256 MB */
			nand@0,0 {
				reg = <0 0 0>; /* CS0, offset 0 */
				nand-bus-width = <8>;
				gpmc,device-width = <1>;
				gpmc,sync-clk-ps = <0>;
				gpmc,cs-on-ns = <0>;
				gpmc,cs-rd-off-ns = <44>;
				gpmc,cs-wr-off-ns = <44>;
				gpmc,adv-on-ns = <6>;
				gpmc,adv-rd-off-ns = <34>;
				gpmc,adv-wr-off-ns = <44>;
				gpmc,we-on-ns = <0>;
				gpmc,we-off-ns = <40>;
				gpmc,oe-on-ns = <0>;
				gpmc,oe-off-ns = <54>;
				gpmc,access-ns = <64>;
				gpmc,rd-cycle-ns = <82>;
				gpmc,wr-cycle-ns = <82>;
				gpmc,wait-on-read = "true";
				gpmc,wait-on-write = "true";
				gpmc,bus-turnaround-ns = <0>;
				gpmc,cycle2cycle-delay-ns = <0>;
				gpmc,clk-activation-ns = <0>;
				gpmc,wait-monitoring-ns = <0>;
				gpmc,wr-access-ns = <40>;
				gpmc,wr-data-mux-bus-ns = <0>;
				ti,nand-ecc-opt= "bch8";
				ti,elm-id = <&elm>;
				/* MTD partition table */
		                /* All SPL-* partitions are sized to minimal length
				 * which can be independently programmable. For
				 * NAND flash this is equal to size of erase-block */
				#address-cells = <1>;
				#size-cells = <1>;
				partition@0 {
					label = "NAND.SPL";
					reg = <0x00000000 0x000020000>;
				};
				partition@1 {
					label = "NAND.SPL.backup1";
					reg = <0x00020000 0x00020000>;
				};
				partition@2 {
					label = "NAND.SPL.backup2";
					reg = <0x00040000 0x00020000>;
				};
				partition@3 {
					label = "NAND.SPL.backup3";
					reg = <0x00060000 0x00020000>;
				};
				partition@4 {
					label = "NAND.u-boot-spl-os";
					reg = <0x00080000 0x00040000>;
				};
				partition@5 {
					label = "NAND.u-boot";
					reg = <0x000C0000 0x00100000>;
				};
				partition@6 {
					label = "NAND.u-boot-env";
					reg = <0x001C0000 0x00020000>;
				};
				partition@7 {
					label = "NAND.u-boot-env.backup1";
					reg = <0x001E0000 0x00020000>;
				};
				partition@8 {
					label = "NAND.kernel";
					reg = <0x00200000 0x00800000>;
				};
				partition@9 {
					label = "NAND.file-system";
					reg = <0x00A00000 0x0F600000>;
				};
			};
		};

		lcdc: lcdc@0x4830e000 {		
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&lcd_pins_default>;
			pinctrl-1 = <&lcd_pins_sleep>;
			status = "okay";
			display-timings {
				800x480p62 {
					clock-frequency = <33000000>;
					hactive 		= <800>;
					vactive 		= <480>;
					hfront-porch	= <35>;
					hback-porch 	= <45>;
					hsync-len 		= <48>;
					vback-porch 	= <23>;
					vfront-porch	= <19>;
					vsync-len 		= <3>;
					hsync-active 	= <1>;
					vsync-active 	= <1>;
				};
			};
		};
	};


	/* 
		The following are used for setting up the 
	*/
	backlight {
		compatible = "pwm-backlight";
		pwms = <&ecap0 0 50000 0>;
		brightness-levels = <0 51 53 56 62 75 101 152 255>;
		default-brightness-level = <8>;
	};
	
		
	/*
		Don't know if these settings are needed
	*/
	panel {
		compatible = "ti,tilcdc,panel";
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&lcd_pins_default>;
		panel-info {
			ac-bias           = <255>;
			ac-bias-intrpt    = <0>;
			dma-burst-sz      = <16>;
			bpp               = <32>;
			fdd               = <0x80>;
			sync-edge         = <0>;
			sync-ctrl         = <1>;
			raster-order      = <0>;
			fifo-th           = <0>;
		};

		display-timings {
			800x480p62 {
				clock-frequency = <33000000>;
				hactive 		= <800>;
				vactive 		= <480>;
				hfront-porch	= <35>;
				hback-porch 	= <45>;
				hsync-len 		= <48>;
				vback-porch 	= <23>;
				vfront-porch	= <19>;
				vsync-len 		= <3>;
				hsync-active 	= <1>;
				vsync-active 	= <1>;
			};
		};
	};
};

#include "tps65217.dtsi"

/* 
	In our case we use TPS65217A specifically for designed for ZCE package
	So for us, the settings are as follows:
		- DCDC1 is set to 1.8V and will never be changed
		- DCDC2 is set at 3.3V and will never be changed
		- DCDC3 is set at 1.1V and will never be changed
			(NOTE - OPP50 will need change in DDR frequency as well - this is
			 something which we may choose to do later)
		- LDO1 is set at 1.8V and can never be changed
		- LDO2 is set at 3.3V and can never be changed
		- LS1/LDO3 is switched off by U-boot and should remain off
		- LS2/LDO4 is switched off by U-boot and should remain off
		
 */
&tps {
	regulators {
		dcdc1_reg: regulator@0 {
			regulator-name = "vdds_ddr";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc2_reg: regulator@1 {			
			regulator-name = "vdd_peripheral";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc3_reg: regulator@2 {			
			regulator-name = "vdd_core";
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <1100000>;
			regulator-max-microvolt = <1100000>;
			regulator-boot-on;
			regulator-always-on;
		};

		ldo1_reg: regulator@3 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-boot-on;
			regulator-always-on;
		};

		ldo2_reg: regulator@4 {
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-boot-on;
			regulator-always-on;
		};

		ldo3_reg: regulator@5 {
			regulator-boot-off;
			regulator-always-off;
		};

		ldo4_reg: regulator@6 {
			regulator-boot-off;
			regulator-always-off;
		};
	};
};


/* 
	These definitions are for the wired Ethernet
	Make sure you override number of slaves and the active slave
 */
&mac {
	slaves = <1>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;	
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
};

/*
	The ethernet phy we use is at address 1 so make sure phy_id is updated.
*/
&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "mii";
};


/* 
	These definitions are for the Touch screen and ADC
 */
&tscadc {
	status = "okay";
	tsc {
		ti,wires = <4>;
		ti,x-plate-resistance = <200>;
		ti,coordinate-readouts = <5>;
		ti,wire-config = <0x00 0x11 0x22 0x33>;
	};

	adc {
		ti,adc-channels = <4 5 6 7>;
	};
};


/* 
	These definitions are for the MMC-0 (SD Card)
	Card detect is GPIO_0_29
 */
&mmc1 {
	status = "okay";
	vmmc-supply = <&dcdc2_reg>;
	bus-width = <4>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_sleep>;
	cd-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;	
};

  • 0 in reply to Santhosh Ramani
    Expert 2765 points

    Hello Miroslav,


    I did trace the problem down to my dts file... the settings for the rx lines were incorrect. The beaglebone common dts file sets the rx lines with pull-ups. I didn't have pull-ups on mine so thats why it didn't get any IP packets.

    This is what I had...this is wrong


                    0x110 (PIN_INPUT  | MUX_MODE0)            /* mii1_rxer */
                    0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txen */
                    0x118 (PIN_INPUT  | MUX_MODE0)            /* mii1_rxdv */
                    0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd3 */
                    0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd2 */
                    0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd1 */
                    0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd0 */
                    0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txclk */
                    0x130 (PIN_INPUT  | MUX_MODE0)            /* mii1_rxclk */
                    0x134 (PIN_INPUT  | MUX_MODE0)            /* mii1_rxd3 */
                    0x138 (PIN_INPUT  | MUX_MODE0)            /* mii1_rxd2 */
                    0x13c (PIN_INPUT  | MUX_MODE0)            /* mii1_rxd1 */
                    0x140 (PIN_INPUT  | MUX_MODE0)            /* mii1_rxd0 */
                  


    This is correct


                    0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxerr.mii1_rxerr */
                    0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txen.mii1_txen */
                    0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxdv.mii1_rxdv */
                    0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd3.mii1_txd3 */
                    0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd2.mii1_txd2 */
                    0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd1.mii1_txd1 */
                    0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* mii1_txd0.mii1_txd0 */
                    0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_txclk.mii1_txclk */
                    0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxclk.mii1_rxclk */
                    0x134 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd3.mii1_rxd3 */
                    0x138 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd2.mii1_rxd2 */
                    0x13c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd1.mii1_rxd1 */
                    0x140 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd0.mii1_rxd0 */

    Anybody else who runs into this issue - please use the beagle bone common file as a reference.

    Thanks for your help Miroslav - sorry for the trouble.

    Regards

     

    Santhosh

  • 0 in reply to Santhosh Ramani
    Intellectual 975 points

    Santhosh, 

    While I haven't seen the same message that you are seeing i.e. "Reply not for us" there is definately a bug in the  SDK 7.0 kernel (kernel 3.12.10)  with and the cpsw that affects DHCP and it doesn't seem to be consistent across boards. 

    See this thread:
    http://e2e.ti.com/support/arm/sitara_arm/f/791/t/338842.aspx

    And this this:
    http://e2e.ti.com/support/arm/sitara_arm/f/791/p/333389/1163824.aspx#1163824

    With my AM335x-EVMSK board and stock SDK 7.0 I can not get ethernet to work at all, whether I'm using DHCP or not and like you it works with SDK 6.
    It's been a while now but I think that moving to a newer kernel with the suggested fix solved the problem but can't be certain, it's been on my to do list to test this again.
    On another note, my BeagleBone Black seems to work fine with stock SDK 7.0 so go figure. 

    I've asked a couple of times when a patch is going to be issued for the SDK and gotten no response. 

    I hope this helps.

    Matt S.