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Are these bits in DDR3 Status Register Sticky?

Chris Wang1
Intellectual 980 points

Are these bits in DDR3 Memory Controller Status Register sticky?

RDLVGATETO

RDLVLTO

WRLVLTO

IFRDY

Assuming I used Full Leveling with incremental leveling turned on, say the read data leveling timeout initially and RDLVLTO is set to zero, does it get set to 1 if the subsequent incremental level converges the read data eye training?  Say my DDR3 PHY is initially lock but somehow loses lock and required lock again, does IFRDY bit goes from 1 to 0 and back to 1?

Thanks,

Chris

  • 0
    TI__Guru* 81335 points

    Hi Chris,

    Looks like this query has been solved offline. Hence closing this thread.

    Thanks.

  • 0 in reply to Raja
    Expert 2125 points

    Hi Rajasekaran,

    We are Facing Certain  issues in accessing the DDR3 Register. I have posted the Query in the bellow link,

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/382674.aspx .

    For us the below setion are set ,

    DDR3 Memory Controller Status Register - RDLVGATETO, RDLVLTO, WRLVLTO, IFRDY(After Gel File Loaded)

    Question:

    Any ideas or solution. It is very urgent.

    Expecting a reply or response .

    Thanks in Advance.

    Regards,

    Avinash N