C6745 EMIFA data rate in async mode

Risto Hedman

Hi,

I'm using EMIFA as an interface to ATA- device, which roughly looks as a FIFO with additional control registers to DSP: I initialize ATA to either read or write and then read or write from/to 8bit data register of ATA. I've realized data xfer with EDMA and loop and both are ok, but very slow, no significant differences in these methods?

I made a minimal test SW only reading ATA in a while loop, nothing else, and got data rate of about 4Mbytes/s (or 250ns between CSs). All waits in EMIFA are off (AWCC=0, CE2CFG=0), DSP is running 300MHz and EMIFA 133MHz. Code is running in L2 and L1 -cache is enabled.

Could you please assist me with this question - what additional settings should I do to increase the speed?

Best Ragards,

Risto

over 11 years ago

0 Sivaraj Kuppuraj over 11 years ago

TI__Mastermind 35645 points

Hi Risto,

We are working on it and will get back to you shortly. It will be addressed soon.

Thanks & regards,

Sivaraj K

0 Titusrathinaraj Stalin over 11 years ago

TI__Guru** 116100 points

Hi Risto,

I believe that EMIFA supports up to 100MHz and EMIFB supports up to 133MHz.

Please refer the C6745 data sheet.

Correct me if I'm wrong.

How did you get clock source for EMIFA ie from SYSCLK3 or DIV4P5?

I've realized data xfer with EDMA and loop and both are ok, but very slow, no significant differences in these methods?

Are you using EDMA for data transfer ?

Please try to change "RDRATE" register efficiently to avoid slower access rate when we use EDMA.

0 Risto Hedman over 11 years ago in reply to Titusrathinaraj Stalin

Expert 1770 points

Dear Titus,

EMIFA should reach 133MHz, too, but according to my tests, problem is not related to EMIFA- clocking but data transfer rate "after EMIFA" - internal bus. I tested with EMIFA 133MHz (DIV4P5) and 75MHz (SYSCLK3 with divider 4) ad times between accessess were 240ns and 340ns respectively. I run loop:

while(1)
uc = *(unsigned char*) (SOC_EMIFA_CS2_ADDR);

I will test EDMA and RDRATE next. Are there any other registers, which could influence the rate data is fetched from EMIFA in a code loop?

BR, risto

0 Titusrathinaraj Stalin over 11 years ago in reply to Risto Hedman

TI__Guru** 116100 points

Hi Risto,

Please check the priority of EDMA,

Please refer the following TI E2E post regarding slow EDMA transfer.

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/331063.aspx

http://processors.wiki.ti.com/index.php/EDMA_Background_Activity_for_OMAP-L1x/C674x/AM1x_Throughput_Measurements

0 RandyP over 11 years ago in reply to Risto Hedman

TI__Guru* 84110 points

Risto,

Can you show us a scope shot with CS, OE, EMA_CLK, at least, showing at least 2 EMIFA read cycles? Also, please show the init code you use for the EMIF registers, hopefully commented, as well as actual dumps of the EMIF registers.

What else do you have on EMIFA, on the other CS lines?

If you do not have SDRAM on EMIFA, please try setting bit 31 of SDCR to 1. This is the SR bit. It would be best to read the SDCR first so you can OR 0x80 to the top byte and write only that top byte, according to some comments in the EMIFA User Guide. I would be interested to see what changes you get in timing, if any.

Regards,
RandyP

0 Risto Hedman over 11 years ago in reply to RandyP

Expert 1770 points

Titus, Randy,

Thank you very much for your comments and advice.

The main reason why EDMA was so slow was my unefficient way to use it, A- sync. When I switched to AB- sync with aCnt=1, bCnt=512 and cCnt=N, the speed rised about a decade.

Thank you again,

Risto

0 Titusrathinaraj Stalin over 11 years ago in reply to Risto Hedman

TI__Guru** 116100 points

Hi Risto,

Sounds good.

Thanks for your update.

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C6745 EMIFA data rate in async mode