In my system OMAP4 GPMC is comment to a FPGA in a 8 bit mode
ie AD0 ~ AD7, ALEn,WEn,OEn,CS2n. I have only this much connection to my FPGA(save my FPGA pin count).
GPMC is configured as
Asynchronous, 8bit, AD muxed, Base Adress 0x0100_0000, Size 16MB
Can i asume since we have only 8 bit adress line in Adress phase(ALE = 0) the memory acess will wrap around on every 256 location. ie 0x01000_0004 and 0x0100_0104 will give same address in address space or any internal exception will occur in OMAP4.
Hello Joseph,
Any external memory or ASIC device attached to the GPMC external interface can be accessed by any device system host within the GPMC 1 Gbyte contiguous address space.
The GPMC 1G byte address space can be divided into a maximum of eight chip-select regions with
programmable base address and programmable CS size. The CS size is programmable from 16M bytes to 128M bytes (must be a power-of-2) and is defined by the mask field. Attached memory smaller than the programmed CS region size is accessed through the entire CS region (aliasing).
Chip-select configuration (base and mask address or any protocol and timing settings) must be performed while the associated chip-select is disabled through the GPMC_CONFIG7_i[6] CSVALID bit (where it stands for the GPMC chip-select value, i = 0 to 7). In addition, a chip-select configuration can only be disabled if there is no ongoing access to that chip-select. This requires activity monitoring of the prefetch or write-posting engine if the engine is active on the chip-select. Also, the write buffer state must be monitored to wait for any posted write completion to the chip-select.
Any access attempted to a nonvalid GPMC address region (CSVALID disabled or address decoding outside a valid chip-select region) is not propagated to the external interface and a GPMC access error is posted. In case of chip-selects overlapping, an error is generated and no access will occur on either chip-select.
The memory size is selected by the "MASKADDRESS" field of GPMC_CONFIG7_i. The base address is configured by BASEADDRESS. The thing to note is that you are specifying bits 29:24 of the address (where bit 0 is the LSB). Essentially your taking the most significant byte of the intended physical address... So let's say we want to make the following mapping:
CS0 -> Size 16MB, Base address 0x0100_0000
CS1 -> Size 64MB, Base address 0x0400_0000
#Q: Can i asume since we have only 8 bit adress line in Adress phase(ALE = 0) the memory access will wrap around on every 256 location. ie 0x01000_0004 and 0x0100_0104 will give same address in address space or any internal exception will occur in OMAP4?
NO, Any chip-select region can be qualified as a memory region to constrain the nADV/ALE signal as Address Latch Enable (ALE active high, default state value at low) during address program access, and the nBE0/CLE signal as Command Latch Enable (CLE active high, default state value at low) during command program access.
Best regards,
Yanko
