Other Parts Discussed in Thread: TMS320DM365
1. Running environment
Hardware: TI tms320dm365
Software: Linux kernel 2.6.32.17
Audio framework: ALSA
Record data flow: Microphone --> (Echo cancel chip)ZL38012 --> McBSP I2S --> ALSA framework.
Playback data flow: ALSA framework --> McBSP I2S --> (Echo cancel chip) --> Speaker。
Remark:
(1) Configuration McBSP to I2S master mode, use McBSP internal clock(SCLKME=0, CLKSM=1).
(2) (Echo cancel chip) ZL38012 was config to I2S slave mode, and it has ADC/DAC functions.
(3) Register a dummy codec device (dummy-CQ93VC) that base on Voice Codec(CQ93VC) ALSA framework.
2. (Echo cancel chip) ZL38012 configure to I2S slave mode
I2S_CLK input frequency 256 KHz (i.e. 32 * sampling frequency).
I2S_FSX input frequency 8 KHz.
3. DM365 configuration
MCBSP_CLKX pin as I2S_CLK.
MCBSP_FSX pin as I2S_LRCK(i.e. word select).
McBSP registers state during the playing is following:
drr: 0x0
dxr: 0x0
spcr: 0x3800001
rcr: 0x0
xcr: 0x450040
srgr: 0x30200fff
mcr: 0x0
pcr: 0xe00
4. Questions
4.1 Why McBSP internal clock is 108 MHz ? DM365 CPU clock frequency 270 MHz, with 24 MHz crystal oscillator.
print kernel log:
static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
// ...
freq = clk_get_rate(dev->clk);
pr_debug("Audio McBSP: into %s, %s, SND_SOC_DAIFMT_CBS_CFS, freq=%u",
__FILE__, __FUNCTION__, freq); /* wenxy debug */
// ...
}
4.2 How to set McBSP internal clock to 66MHz ?
How to set MCBSP_CLKX output 256 KHz, MCBSP_FSX output 8 KHz ?
MCBSP_CLKX output frequency = 108 MHz / CLKGDV = 108 MHz / (255 + 1) = 422 KHz.
MCBSP_FSX output frequency12.7 KHz.
PLLDIV4 register value is 0x00008003, I modify PLLDIV4 register value to 0x00008006, but no effect.
4.3 Playback wave file, how to get sound parameters (sampling frequency, channel, sampling bits) in McBSP driver ?
Could please someone who is familiar with the sound/soc driver for the dm365 give me any advice
how to make the McBSP to behave properly?
