PCIe SERDES_CLK AC coupling cap value

hi it is 270pF ... and it is revD. strange...

Stephen,

As Eason stated, the DM814x EVM SERDES_CLKN/P capacitors are 270pF (the typical value from the datasheet).

I think you are looking at the DM816x EVM, where the SERDES_CLKN/P capacitors are 100nF (.1uF). Even there, the DM816x datasheet should be the correct one (vs DM816x EVM), as in DM816x datasheet we have:

The value of this capacitor depends on several factors including differential input clock swing. For a 100-MHz differential clock with an approximate 1-V voltage swing, the recommended typical value for the SERDES clock AC coupling capacitors is 270 pF. Deviating from this recommendation can result in the reduction of clock signal amplitude or lowering the noise rejection characteristics.

Regards,
Pavel

Hi Pavel

The revD schematic for the TMDXEVM8148 from Mistral's website shows the following PCIe REFCLK circuitry:

This is not the circuitry that Eason posted.  I'd like to know where Eason's circuitry originated from, as it also has a 100ohm termination resistor that is not mentioned in any DM814x documentation that I have seen.

thanks

Stephen,

From where you get this schematics?

I am using the below link:

http://www.mistralsolutions.com/pes-support/support-downloads/tmdxevm8148.html#

Downloads for TMDXEVM8148 – Base Board -> Rev - D -> Schematics -> PDF Format -> MS_TI_DM814x_BB_REVD_SCH.pdf (Rev D, version 0.06)

3731.MS_TI_DM814x_BB_REVD_SCH.pdf

In this schematics, I can see only the 270pF SERDES_CLKN/P capacitors.

Regards,
Pavel

Hi Pavel

Eason pointed out that I was looking at a different part of the schematic.  I did not realize there was a clock generator driving both the PCIe slot and the DM814x.  It makes sense now

thanks