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Device configuration through OMPA 4460 GMPC bus

Namrata Sharma
Prodigy 30 points
Other Parts Discussed in Thread: 4460

Hello All

   I am new in OMAP, I want to communicate OMAP 4460 to three device NAND flash, SRAM and LPDDR  through FPGA.

In the case of SRAM and LPDDR we need to design controller can you plz telll me how to design and in case of NAND flash how to configure NAND flash here i need to implement only bypass logic in FPGA.

 In the case of SRAM add/data bus is 18[0:17] bit but as per OMAP 4460 data sheet its provide only 16[0:15]bit so can you plz suggest how to communicate.

Ple tell me also GPMC modes and how it is useful in external memory communication.

How many register we can use for configuration a device.    

  Please give reply 

Thanks

   

  • 0
    TI__Mastermind 29520 points

    Hello Namrata,

    #Q1: can you plz telll me how to design and in case of NAND flash how to configure NAND flash here i need to implement only bypass logic in FPGA.

    - At first,  I suggest you familiarizing with GPMC module in OMAP4460. Refer to GPMC chapter in OMAP44600 TRM.

    The GPMC configuration currently happening through u-boot/x-loader, Kernel only reads the configuration done by u-boot and uses it to find mapped/configured physical address and maps it to kernel virtual.

    You can design GPMC driver to interface FPGA as refer to the existing GPMC configuration setting in u-boot ("arch/arm/cpu/arm_cortexa8/omap3/mem.c" and function  "gpmc_init"  

     * (): init gpmc bus
     * Init GPMC for x16, MuxMode (SDRAM in x32).
     * This code can only be executed from SRAM or SDRAM.).

    #Q2: In the case of SRAM add/data bus is 18[0:17] bit but as per OMAP 4460 data sheet its provide only 16[0:15]bit so can you plz suggest how to communicate.

    - The general-purpose memory controller (GPMC) is an unified memory controller dedicated to interfacing
    external memory devices:
    • Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
    • Asynchronous, synchronous, and page mode (available only in nonmuxed mode) burst NOR flash
    devices
    • NAND flash
    • Pseudo-SRAM devices

    I would like to notice you:
    The GPMC can communicate with a wide range of external devices:
    • External asynchronous or synchronous 8-bit wide memory or device (nonburst device)
    • External asynchronous or synchronous 16-bit wide memory or device
    • External 16-bit nonmultiplexed device with limited address range (2KB)
    • External 16-bit address/data-multiplexed NOR flash device
    • External 8-bit and 16-bit NAND flash device
    • External 16-bit pseudo-SRAM (pSRAM) device
    The main features of the GPMC are:
    • 8- or 16-bit-wide data path to external memory device

    #Q3: Ple tell me also GPMC modes and how it is useful in external memory communication.

    - There are three possible GPMC external connections options:

    1. A connection between the GPMC and a 16-bit synchronous address/data-multiplexed (or AAD-multiplexed, but this protocol use less address pins) external memory device

    2. A connection between the GPMC and a 16-bit synchronous nonmultiplexed external memory device

    3. A connection between the GPMC and a 16-bit NAND device

    Have a detail look on the section 15.4.6 GPMC Use Cases And Tips in GPMC chapter in TRM.

    See the application note - https://www.spansion.com/Support/Application%20Notes/Iface_Flash_TI_OMAP_Proc_AN.pdf


    #Q4: How many register we can use for configuration a device.   

    - Refer to generic GPMC Linux driver - Linux/arch/arm/mach-omap2/gpmc.c - http://lxr.free-electrons.com/source/arch/arm/mach-omap2/gpmc.c

    For more information see the link:

    http://processors.wiki.ti.com/index.php/Tips_for_configuring_OMAP35x_and_AM-DM37x_GPMC_registers

    Best regards,

    Yanko