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some questions about the image_processing demo

Other Parts Discussed in Thread: SYSBIOS

Hi,

I tried to modify the demo in mcsdk_2_01_02_06\demos\image_processing\ipc\evmc6657l, so I created a new project in my own workspace and the copied all files form the demo to the new project. However, the new project couldn't compile and show: 

I checked the differences between the two projects, and found the demo's platform is demos.image_processing.ipc.evmc6657l.platform while my project's platform is ti.platforms.evm6657. I tried to change my platform but failed. How can I use demos.image_processing.ipc.evmc6657l.platform ?

  • Besides, the resourcemgr.c file in the demo contain these codes:

    /* PASS RL file */
    #include <ti/csl/cslr_pa_ss.h>

    /* Firmware images */
    #include <ti/drv/pa/fw/classify1_bin.c>
    #include <ti/drv/pa/fw/classify2_bin.c>
    #include <ti/drv/pa/fw/pam_bin.c>

    I noticed these header files are only valid for C6670 and C6678, why can the demo compiled? 

  • Yuxin Yuan,

    When you create new project should be choose the relevant device or board family correctly. And also check the dependent packages. Please compare the original project settings with your newly created one. I can suggest you, instead of creating new one, just take the copy from an original project and add the source files to local folder for modification if needed.

    Here, Master project does not use the resourcemgr.c file, you can see that file is excluded from the project.

    Here, you can see the location of the platform

      

    Refer the excluded file, right click on the source file and find the options. 

  • Pubesh,

    Thank you for your suggestions and I have followed them.

    I also wonder what are the functions of Cache_inv and Cache_wb, what the parameters mean, and when should I use them?

  • Yuxin Yuan,

    Please find the details for Cache_inv and Cache_wb APIs.

    Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);

    • Invalidate the range of memory within the specified starting address and byte count.
    • The range of addresses operated on gets quantized to whole cache lines in each cache.
    • All lines in range are invalidated for all the 'type' caches.

    Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait); 

    • Writes back the range of memory within the specified starting address and byte count.
    • The range of addresses operated on gets quantized to whole cache lines in each cache.
    • All lines within the range are left valid in the 'type' caches and the data within the range will be written back to the source memory.

    blockPtr  -  start address of range to be invalidated. 
    byteCnt    -  number of bytes to be invalidated. 
    type          -  bit mask of Cache type. 
    wait          -  wait until the operation is completed.

    Please have a look at the section "Cache Interface Functions" in the TI SYS/BIOS Real-time Operating System

    User's Guide.

  • I used the following codes to test NDK transport time:

    ts1 = (Int32) Timestamp_get32();

    /*
    * Read in the data. We should probably read this in little chunks in case ContentLength was a lie or
    * there is an error...
    */
    len = 0;
    while (len < ContentLength ){
    /* This is a work around for IE 7.0 and 8.0 */
    len = recv( htmlSock, gRxBuffer, ContentLength, MSG_WAITALL );
    }
    // printf("get image!\n");
    ts2 = (Int32) Timestamp_get32();
    ts2 = ts2 - ts1;
    processing_time = ((double)ts2 / (double)freq.lo) * 1000;
    printf("NDK time = %f\n",processing_time);

    Why I got different result each time since the code and data never changed? And sometimes the result was below zero?

  • Yuxin Yuan,

    Please check the sequence as per below,

    Types_FreqHz freq;
    Int32 ts1, ts2;

    double * processing_time;

    Timestamp_getFreq(&freq);

    ts1 = (Int32) Timestamp_get32();

    ----------------------

    ----------------------

    ts2 = (Int32) Timestamp_get32();
    ts2 = ts2 - ts1;
    *processing_time = ((double)ts2 / (double)freq.lo) * 1000;

    Note: If you have new query, create the new thread.

  • I wanted to do malloc in slave core, but the console show that:

    ti.sysbios.heaps.HeapMem: line 307: out of memory: handle=0x81edc0, size=2568

    I thought maybe the size of heap is too small, refer to the .cfg file in master core, I changed the heap configuration in slave core:

    var heapMemParams = new HeapMem.Params;
    heapMemParams.size = 0x800000;
    heapMemParams.sectionName = "systemHeapSlave";
    var heap0 = HeapMem.create(heapMemParams);
    Memory.defaultHeapInstance = heap0;

    ........

    Program.sectMap["systemHeapSlave"] = "DDR3";

    When I rerun the project, the Core0 aborted and the console printed:
    A0=0x0 A1=0x2c
    A2=0x0 A3=0x3b3d3d
    A4=0x80000088 A5=0x0
    A6=0x800031bc A7=0x0
    A8=0x0 A9=0x2
    A10=0x80001620 A11=0x800031bc
    A12=0x878ff0 A13=0x9007f5c0
    A14=0x0 A15=0x0
    A16=0x80001644 A17=0x0
    A18=0x80001618 A19=0x20
    A20=0x851ee4 A21=0x0
    A22=0xbe A23=0x0
    A24=0x470 A25=0x23
    A26=0x8800 A27=0x0
    A28=0x400 A29=0x1
    A30=0x400 A31=0x0
    B0=0x80001620 B1=0x0
    B2=0x0 B3=0x9002c6e0
    B4=0x9007f5c0 B5=0x0
    B6=0x80003208 B7=0xc
    B8=0x1c B9=0x30
    B10=0x8000323c B11=0x80003208
    B12=0x0 B13=0x0
    B14=0x87d630 B15=0x80003158
    B16=0x90081a30 B17=0x0
    B18=0x81000000 B19=0x3feffc5c
    B20=0x1 B21=0x90066a00
    B22=0xf B23=0x0
    B24=0x0 B25=0x8e0000
    B26=0x0 B27=0x1
    B28=0x0 B29=0x1
    B30=0x0 B31=0x0
    NTSR=0x1020f
    ITSR=0x20d
    IRP=0x9007447a
    SSR=0x0
    AMR=0x0
    RILC=0x0
    ILC=0x0
    Exception at 0x3b3d3c
    EFR=0x2 NRP=0x3b3d3c
    Internal exception: IERR=0x1
    Instruction fetch exception
    ti.sysbios.family.c64p.Exception: line 255: E_exceptionMin: pc = 0x003b3d3c, sp = 0x80003158.
    To see more exception detail, use ROV or set 'ti.sysbios.family.c64p.Exception.enablePrint = true;'
    xdc.runtime.Error.raise: terminating execution

    The Core0 aborted around MessageQ_creat(), how to correct it?

  • Yuxin Yuan,

    What is the status of your  issues posted previous. We gave the solution, is it ok?. Your are keeping on jumping to next issue and not relevant with the old one. Please make sure when you are getting new issue, please post new thread instead of previous issue discussion. The multicore navigator initialization calls are supported on Core0 only.  Your issue is related with memory, what are the changes made by you.  Do the power cycle for the EVM and run the suitable project on core0 and other project on core1, core2.

  • Pubesh ,

    I have taken your solution and copied the demo to make some changes. Thanks very much.

    Since my new issue is about the image processing demo, so I posted it here. I'm so sorry to trouble you. I will create a new thread to illustrate it.

    Regards.