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UART with EDMA3 at 2mbps baud rate

Jam Akh
Intellectual 615 points
Other Parts Discussed in Thread: OMAPL138

Hi,

I am working on UART for Omapl138.I am using EDMA3 to receive data from UART.  I am using linking property of EDMA3. So once I programmed,EDMA3 param will continue to update and EDMA wil continue to receive data from UART FIFO.

The problem is,my EDMA work at 1.5mbps but it does not work at 2mbps or higher baud rate.At 2mbps EDMA3 is not able to get data from UART FIFO very quickly so FIFO over run occurs.As FIFO over run occurs,EDMA stops working as it does not pick erroneous data as mentioned in UART reference manual.

some importent setting are

acnt =1, bcnt= 6000, cnt =1

UART FIFO triger level = 1 but changing trigger level does not solve the problem.

I am using my own softwares.

is DMA is not capable to pick data so quickly?

Any help ?

Thanks&Regards

Jam

  • 0
    Intellectual 615 points

    Hi

    Any one from TI to help me?

    Thanks

    Jam

  • 0
    TI__Mastermind 35645 points

    Hi Jam,

    Thanks for your post.

    In my understanding, DMA is capable to pick data at higher baudrates, but you need to configure the divisor value and desired baud rates so that, to produce a appropriate baud clock which needs to be compliant as per the omapl138 specifications. Usually, the UART has a programmable baud generator which takes an input clock and divides it by a divisor in the range between 1 and (216 - 1) to produce a baud clock (BCLK) and the the frequency of BCLK is sixteen times (16x) the baud rate ( each received or transmitted bit lasts 16 BCLK cycles) or thirteen times (13x) the baud rate (each received or transmitted bit lasts 13 BCLK cycles). When the UART is receiving, the bit is sampled in the 8th BCLK cycle for 16x over sampling mode and on the 6th BCLK cycle for 13x over-sampling mode. Again, you can select the 16x or 13x reference clock by configuring the OSM_SEL bit in the mode definition register (MDR).

    For the divisor value formula to calculate and more details, please refer section 32.2.1 from the omapl138 TRM as below:

    http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 615 points

    Hi Sivaraj,

    Thanks for your reply.

    Yes I understand your concern about baud rate calculation .In 2mbps case,

    divisor= 132000000(uart freq)/2000000(baud rate)/13(13x)=5.07 so divisor is fine.

    I am looking into this document SPRAAG8 2006TMS320TCI6482 EDMA3 Performance and if we see 
    Transfer Overhead for MCBSP, it is 200cpu cycles for transfer to DDR2. and transfer delay is not only latency.so this make me think that in UART case acnt= 1 so DMA is not able to pick data as quickly so FIFO over run occurs.As  there is no software overhead due to linking so all things goes to hardware.
    Thanks
    Jam